Xilinx RocketIO User Manual page 25

List of Available Ports
Table 1-5: GT_CUSTOM
GT_INFINIBAND, and GT_XAUI Primitive Ports (Continued)
Port
REFCLKSEL
RXBUFSTATUS
(3)
RXCHARISCOMMA
(3)
RXCHARISK
RXCHECKINGCRC
RXCLKCORCNT
RXCOMMADET
RXCRCERR
(3)
RXDATA
(3)
RXDISPERR
RXLOSSOFSYNC
(4)
RXN
RocketIO™ Transceiver User Guide
UG024 (v2.3.2) June 24, 2004
(1)
, GT_AURORA, GT_FIBRE_CHAN
Port
I/O
Size
I 1 Selects the reference clock to use:
Low = selects REFCLK if REF_CLK_V_SEL = 0
High = selects REFCLK2 if REF_CLK_V_SEL = 0
See "REF_CLK_V_SEL," page
O 2 Receiver elastic buffer status. Bit 1 indicates if an overflow/underflow error
has occurred when asserted High. Bit 0 indicates that the buffer is at least half-
full when asserted High.
O 1, 2, 4 Similar to RXCHARISK except that the data is a comma.
O 1, 2, 4 If 8B/10B decoding is enabled, it indicates that the received data is a
K-character when asserted High. Included in Byte-mapping. If 8B/10B
decoding is bypassed, it remains as the first bit received (Bit "a") of the 10-bit
encoded data (see
O 1 CRC status for the receiver. Asserts High to indicate that the receiver has
recognized the end of a data packet. Only meaningful if RX_CRC_USE =
TRUE.
O 3 Status that denotes occurrence of clock correction or channel bonding. This
status is synchronized on the incoming RXDATA. See
page 77.
O 1 Signals that a comma has been detected in the data stream.
To assure signal is reliably brought out to the fabric for different data paths, this
signal may remain High for more than one USRCLK/USRCLK2 cycle.
O 1 Indicates if the CRC code is incorrect when asserted High. Only meaningful if
RX_CRC_USE = TRUE.
O 8, 16, 32 Up to four bytes of decoded (8B/10B encoding) or encoded (8B/10B bypassed)
receive data.
O 1, 2, 4 If 8B/10B encoding is enabled it indicates whether a disparity error has
occurred on the serial line. Included in Byte-mapping scheme.
O 2 Status related to byte-stream synchronization (RX_LOSS_OF_SYNC_FSM)
If RX_LOSS_OF_SYNC_FSM = TRUE, RXLOSSOFSYNC indicates the
state of the FSM:
Bit 1 = Loss of sync (High)
Bit 0 = Resync state (High)
If RX_LOSS_OF_SYNC_FSM = FALSE, RXLOSSOFSYNC indicates:
Bit 1 = Received data invalid (High)
Bit 0 = Channel bonding sequence recognized (High)
I 1 Serial differential port (FPGA external)
www.xilinx.com
1-800-255-7778
(2)
, GT_ETHERNET
Definition
selects BREFCLK if REF_CLK_V_SEL = 1
selects BREFCLK2 if REF_CLK_V_SEL = 1
32.
Figure 2-14, page 66).
(2)
,
"RXCLKCORCNT,"
R
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