Xilinx RocketIO User Manual page 30

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Table 1-6: RocketIO Transceiver Attributes (Continued)
Attribute
CLK_COR_INSERT_IDLE_FLAG
CLK_COR_KEEP_IDLE
CLK_COR_REPEAT_WAIT
CLK_COR_SEQ_*_*
CLK_COR_SEQ_2_USE
CLK_COR_SEQ_LEN
CLK_CORRECT_USE
COMMA_10B_MASK
CRC_END_OF_PKT
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TRUE/FALSE controls whether RXRUNDISP input status denotes running
disparity or inserted-idle flag.
FALSE: RXRUNDISP denotes running disparity when RXDATA is decoded
data.
TRUE: RXRUNDISP is raised for the first byte of each inserted (repeated) clock
correction ("Idle") sequence (when RXDATA is decoded data).
TRUE/FALSE controls whether or not the final byte stream must retain at least one
clock correction sequence.
FALSE: Transceiver can remove all clock correction sequences to further
recenter the elastic buffer during clock correction.
TRUE: In the final RXDATA stream, the transceiver must leave at least one
clock correction sequence per continuous stream of clock correction
sequences.
Integer 0 - 31 controls frequency of repetition of clock correction operations.
This attribute specifies the minimum number of RXUSRCLK cycles without clock
correction that must occur between successive clock corrections. If this attribute is
zero, no limit is placed on how frequently clock correction can occur.
11-bit vectors that define the sequence for clock correction. The attribute used
depends on the CLK_COR_SEQ_LEN and CLK_COR_SEQ_2_USE.
TRUE/FALSE controls use of second clock correction sequence.
FALSE: Clock correction uses only one clock correction sequence defined by
CLK_COR_SEQ_1_1...4.
TRUE: Clock correction uses two clock correction sequences defined by:
CLK_COR_SEQ_1_1...4 and
CLK_COR_SEQ_2_1...4
as further constrained by CLK_COR_SEQ_LEN.
Integer that defines the length of the sequence the transceiver matches to detect
opportunities for clock correction. It also defines the size of the correction, since the
transceiver executes clock correction by repeating or skipping entire clock
correction sequences.
TRUE/FALSE controls the use of clock correction logic.
FALSE: Permanently disable execution of clock correction (rate matching).
Clock RXUSRCLK must be frequency-locked with RXRECCLK in this case.
TRUE: Enable clock correction (normal mode).
This 10-bit vector defines the mask that is ANDed with the incoming serial bit
stream before comparison against PCOMMA_10B_VALUE and
MCOMMA_10B_VALUE.
NOTE: This attribute is only valid when CRC_FORMAT = USER_MODE.
K28_0, K28_1, K28_2, K28_3, K28_4, K28_5, K28_6, K28_7, K23_7, K27_7,
K29_7, K30_7. End-of-packet (EOP) K-character for USER_MODE CRC. Must be
one of the 12 legal K-character values.
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Chapter 1: RocketIO Transceiver Overview
Description
RocketIO™ Transceiver User Guide
UG024 (v2.3.2) June 24, 2004