Cpc Signals - Sma[5,4,2,1], Smab[5,4,2,1]; Table 30. Cpc Signal To So-Dimm Mapping - Intel 852GME Design Manual

R
6.3.5. CPC Signals – SMA[5,4,2,1], SMAB[5,4,2,1]
The GMCH/MCH chipset CPC (clock-per-command) signals, SMA[5,4,2,1] and SMAB[5,4,2,1]are
"clocked" into the DDR SDRAM devices using clock signals SCK/SCK#[5:0]. The GMCH/MCH drives
the CPC and clock signals together, with the clocks crossing in the valid command window. The
GMCH/MCH provides one set of CPC signals per SO-DIMM slot.
Refer to Table 23 for the CKE and CS# signal to SO-DIMM mapping.

Table 30. CPC Signal to SO-DIMM Mapping

Signal
SMA[1]
SMA[2]
SMA[4]
SMA[5]
SMAB[1]
SMAB[2]
SMAB[4]
SMAB[5]
The CPC signal routing should transition from an external layer to an internal signal layer under the
GMCH/MCH. Keep to the same internal layer until transitioning back out to an external layer to connect to
the appropriate pad of the SO-DIMM connector and the parallel termination resistor. If the layout requires
additional routing before the termination resistor, return to the same internal layer and transition back out
to an external layer immediately prior to parallel termination resistor.
External trace lengths should be minimized. Intel suggests that the parallel termination be placed on both
sides of the board to simplify routing and minimize trace lengths. All internal and external signals should
be ground reference to keep the path of return current continuous. Intel suggests that all CPC signals be
routed on the same internal layer.
Resistor packs are acceptable for the parallel (Rt) CPC termination resistors. Figure 37 and Table 31 below
depict the recommended topology and layout routing guidelines for the DDR-SDRAM CPC signals.
® ®
Intel 852GME, Intel 852GMV and Intel
System Memory Design Guidelines (DDR-SDRAM)
Relative To SO-DIMM Pin
SO-DIMM0 AD14
SO-DIMM0 AD13
SO-DIMM0 AD11
SO-DIMM0 AC13
SO-DIMM1 AD16
SO-DIMM1 AC12
SO-DIMM1 AF11
SO-DIMM1 AD10
®
852PM Chipset Platforms Design Guide
101