Usb Connect Ors; Lpc Super I / O ( Si O) / Lpc Slot; Serial, I Rda; Bi Os Firm Ware Hub ( Fwh) - Intel Core 2 Duo User Manual

The I nt el
parallel I DE channel and t he serial ATA channels. A device can be powered down by
soft ware and t he port can t hen be disabled, allowing rem oval and insert ion of a new
device. The parallel I DE device should be powered from t he power connect or, J4J2, on
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t he I nt el
requires cust om er- developed soft ware support .
Deskt op hard drives m ust be powered using t he ext ernal ATX power supply, not t he
onboard power supply.
The I nt el
providing great er perform ance and reliabilit y t hrough feat ures such as Nat ive
Com m and Queuing ( NCQ) and RAI D 0/ 1. For m ore inform at ion about I nt el® Mat rix
St orage Technology, refer t o I nt el's websit e at :
ht t p: / / www.int el.com / design/ chipset s/ m at rixst orage_sb.ht m
3 .4 .2 .6 USB Con n e ct or s
The I CH7- M provides a t ot al of eight USB 2.0 port s. Three port s are rout ed t o a t riple-
st ack USB connect or at J3A1. Two port s are rout ed t o a com binat ion RJ- 45/ dual USB
connect or at J5A1B. Three port s are rout ed t o USB front panel headers at J6H2 and
J7E2.
3 .4 .2 .7 LPC Su pe r I / O ( SI O) / LPC Slot
An SMSC LPC47N207 serves as t he SI O on t he I nt el
plat form . Shunt ing t he j um per at J7E3 t o t he 2- 3 posit ions can disable t he SI O by
holding it in reset . This allows ot her SI O solut ions t o be t est ed in t he LPC slot at J8F1.
A sideband header is provided at J9G2 for t his purpose. This sideband header also has
signals for LPC power m anagem ent . I nform at ion on t his header is on sheet 35 of t he
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I nt el 945GME Express Chipset schem at ics and is det ailed in t he " LPC Slot and
Sideband Header Specificat ion" ( refer t o
3 .4 .2 .8 Se r ia l, I r D A
The SMSC SI O incorporat es a serial port , and I rDA ( I nfrared) , as well as general
purpose I Os ( GPI O) . The serial port connect or is provided at J2A2A, and t he I rDA
t ransceiver is locat ed at U4A1. The I rDA t ransceiver on I nt el
support s bot h SI R ( slow I R) and CI R ( Consum er I R) . The opt ion t o select bet ween t he
t wo is support ed t hrough soft ware and GPI O pin on t he SI O.
3 .4 .2 .9 BI OS Fir m w a r e H u b ( FW H )
The 8 Mbit Flash device used on t he I nt el
and video BI OS as well as an I nt el Random Num ber Generat or ( RNG) is a socket ed
E82802AC8 a 32- pin PLCC package. The reference designat or locat ion of t he FWH
device is U8G1. The BI OS can be upgraded using an MS- DOS* based ut ilit y and is
addressable on t he LPC bus off of t he I CH7- M.
3 .4 .2 .1 0 Sy st e m M a n a ge m e n t Con t r olle r ( SM C) / Ke yboa r d Con t r olle r
The Hit achi* H8S/ 2104V serves as bot h SMC and KBC for t he plat form . The SMC/ KBC
cont roller support s t wo PS/ 2 port s, bat t ery m onit oring and charging, EMA support ,
wake/ runt im e SCI event s, and power sequencing cont rol. The t wo PS/ 2 port s on t he
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I nt el 945GME Express Chipset are for legacy keyboard and m ouse. The keyboard
plugs int o t he bot t om j ack and t he m ouse plugs int o t he t op j ack at J1A1. Scan m at rix
keyboards can be support ed via an opt ional connect or at J9E1.
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I nt el Core 2 Duo processor wit h t he Mobile I nt el
Manual
26
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945GME Express Chipset also support s 'ATA swap' capabilit y for bot h t he
945GME Express Chipset t o ut ilize t he hot swap feat ure. This feat ure
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945GME Express Chipset includes I nt el® Mat rix St orage Technology,
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945GME Express Chipset
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I n t e l 9 4 5 GM E Ex pr e ss Ch ipse t —Th e or y of Ope r a t ion
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945GME Express Chipset
Table 3, " Relat ed Docum ent s" on page
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945GME Express Chipset
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945GME Express Chipset t o st ore syst em
Order Num ber: 317443- 001US
15) .
May 2007