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Operating Mode Selection
5.2
Configuring a Single-Ended Input
For a single-ended clock input, remove the crystal if the board already has one. Use the SMA connector
J101 for a single-ended input clock. Place a 50-Ω resistor in R69 if a signal generator provides the clock,
and if the signal generator requires a 50-Ω load for its operation. If another board or the LVCMOS buffer
provides the input clock, do not place any resistor here. For an external clock, set the input signal swing to
2.5V (and not 3.3V, as the input is only compatible with 2.5-V input signals), and set the input signal
frequency to 25 MHz.
Capacitor C61 (100 nF) is necessary for ac coupling,
6
Operating Mode Selection
The CDCM9102 is a PLL-based device and offers multiple modes of operation.
6.1
Output Buffer Type Selection
JP16 (OS1) and JP15 (OS0) are the jumpers for output buffer selection (LVCMOS, LVDS, or LVPECL).
Each output pair provides two, in-phase LVCMOS clocks.
Table 1
shows the output buffer options.
6.2
Using ENABLE and RESET Pins
JP22 (CHIP_DISABLE) is the jumper for the OE pin. This pin has an internal 150-kΩ pullup resistor; use
the internal pullup resistor only for logic 1.
Table 2
summarizes the power-down configuration.
OE (Pin 7)
0
1
4
CDCM9102EVM Clock Evaluation Module
C61
100 nF
J101
R69
50
W
(Optional)
Figure 3. Single-Ended Connection Configuration
Table 1. Output Buffer Options
Control Inputs
OS1
OS0
0
0
0
1
1
0
1
1
(1)
A bypassed output (same as the reference clock frequency) is only
available with LVPECL outputs.
Table 2. Power-Down Configuration
Mode
Power down
Normal
Copyright © 2012, Texas Instruments Incorporated
(Figure
3).
C
IN
8 pF
CDCM9102
(1)
Output Type
LVCMOS, OSC_OUT Off
LVDS, OSC_OUT Off
LVPECL, OSC_OUT Off
LVPECL, OSC_OUT On
Device Core
Power down
Active
www.ti.com
Output
Hi-Z
Active
SCAU048 – March 2012
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