Timing Of I 2 C Interrupt Request (Intiic0) Occurrence - NEC 78K0R/KE3 User Manual

16-bit single-chip microcontrollers
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2
12.5.18 Timing of I
C interrupt request (INTIIC0) occurrence
The timing of transmitting or receiving data and generation of interrupt request signal INTIIC0, and the value of the
IICS0 register when the INTIIC0 signal is generated are shown below.
Remark
ST:
AD6 to AD0: Address
R/W:
ACK:
D7 to D0:
SP:
518
CHAPTER 12 SERIAL INTERFACE IIC0
Start condition
Transfer direction specification
Acknowledge
Data
Stop condition
User's Manual U17854EJ9V0UD

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