Table of Contents
Advertisement
14.5.7 Forced termination by software
After DSTn is set to 0 by software, it takes up to 2 clocks until a DMA transfer is actually stopped and DSTn is set
to 0. To forcibly terminate a DMA transfer by software without waiting for occurrence of the interrupt (INTDMAn) of
DMAn, therefore, perform either of the following processes.
<When using one DMA channel>
• Set DSTn to 0 (use DRCn = 80H to write with an 8-bit manipulation instruction) by software, confirm by polling
that DSTn has actually been cleared to 0, and then set DENn to 0 (use DRCn = 00H to write with an 8-bit
manipulation instruction).
• Set DSTn to 0 (use DRCn = 80H to write with an 8-bit manipulation instruction) by software and then set DENn
to 0 (use DRCn = 00H to write with an 8-bit manipulation instruction) two or more clocks after.
<R>
<When using both DMA channels>
• To forcibly terminate DMA transfer by software when using both DMA channels (by setting DSTn to 0), clear the
DSTn bit to 0 after the DMA transfer is held pending by setting the DWAIT0 and DWAIT1 bits of both channels to
1. Next, clear the DWAIT0 and DWAIT1 bits of both channels to 0 to cancel the pending status, and then clear
the DENn bit to 0.
Remarks 1. n: DMA channel number (n = 0, 1)
Figure 14-13. Forced Termination of DMA Transfer (1/2)
Example 1
DSTn = 0
No
DSTn = 0 ?
Yes
DENn = 0
2. 1 clock: 1/f
(f
: CPU clock)
CLK
CLK
CHAPTER 14 DMA CONTROLLER
User's Manual U17854EJ9V0UD
Example 2
DSTn = 0
2 clock wait
DENn = 0
571
Advertisement
Table of Contents
