Cpu - Toshiba TLCS-900/H1 Series Data Book

3. OPERATION
This section describes the basic components, functions and operation of the TMP92CH21.

3.1 CPU

The TMP92CH21 contains an advanced high-speed 32-bit CPU(900/H1 CPU)
3.1.1 CPU Outline
900/H1 CPU is high-speed and high-performance CPU based on 900/L1 CPU. 900/H1 CPU has
expanded 32-bit internal data bus to process Instructions more quickly.
Outline of 900/H1 CPU are as follows:
3.1.2 Reset Operation
When resetting the TMP92CH21 microcontroller, ensure that the power supply voltage is
within the operating voltage range, and that the internal high-frequency oscillator has stabilized.
Then hold the /RESET input Low for at least 20 system clocks(16µs at 40MHz).
At reset, since the clock doubler(PLL) is bypassed and clock-gear is set to 1/16,
system clock operates at 1.25MHz(fc=40MHz).
When the Reset has been accepted, the CPU performs the following:
• Sets the Program Counter (PC) as follows in accordance with the Reset Vector stored
at address FFFF00H~FFFF02H:
PC<0~7>
PC<8~15> ← data in location FFFF01H
PC<16~23> ← data in location FFFF02H
• Sets the Stack Pointer (XSP) to 00000000H.
• Sets bits <IFF0 to IFF2> of the Status Register (SR) to 111 (thereby setting the Interrupt
Level Mask Register to level 7).
• Clears bits <RFP0 to RFP1> of the Status Register to 00 (thereby selecting Register
Parameter
Width of CPU Address Bus
Width of CPU Data Bus
Internal Operating Frequency
Minimum Bus Cycle
Internal RAM
Internal Boot-ROM
Internal I/O
External Device
Minimum Instruction
Execution Cycle
Conditional Jump
Instruction Queue Buffer
Instruction Set
CPU mode
Micro DMA
← data in location FFFF00H
900/H1 CPU
max.20MHz (at fc=40MHz)
1-clock access(50ns)
32-bit 1-clock access
32-bit 2-clock access
8/16-bit 2-clock access
8/16-bit 5 to 6-clock access
8/16/32-bit 2-clock access
(can insert some waits)
1-clock(50ns)
2-clock(100ns)
Compatible with
TLCS-900/L1,TLCS-900/H2
(LDX instruction is deleted)
Only maximum mode
8-channel
92CH21 - 12
24-bit
32-bit
12-byte
TMP92CH21