Toshiba TLCS-900/H1 Series Data Book page 186

(07F0H) After reset: 0000 00**B
USBINTFR1
7
bit symbol NT_URST_STR N T_URST_END INT_SUS
R/W R/W
･INT_URST_STR (bit7)
0:INT_URST_STR not generated
1:INT_URST_STR
This is a flag register for INT_URST_STR (USB starting interrupt by USB_RESET ).
This is set to "1" when USB controller started to receive "bus reset" signal from USB-host.
An application program has to initialize whole USBC by this interrupt.
･INT_URST_END (bit6)
0:INT_URST_END not generated
1:INT_URST_END
This is a flag register for INT_URST_END (USB termination interrupt by USB_RESET ).
This is set to "1" when USB controller received "bus reset termination" signal from USB-host.
･INT_SUS (bit5)
0:INT_SUS not generated
1:INT_SUS generated
This is a flag register for INT_SUS (USB suspend interrupt).
This is set to "1" when USB changed to "suspend status".
･INT_RESUME (bit4)
0:INT_RESUME not generated
1:INT_RESUME
This is a flag register for INT_RESUME (USB resume interrupt).
This is set to "1" when USB changed to "resume status".
･INT_CLKSTOP (bit3)
0:INT_CLKSTOP not generated
1:INT_CLKSTOP
This is a flag register for INT_CLKSTOP (USB enabled to stop clock supplying interrupt).
This is set to "1" when USB changed to "suspend status" and enabled to stop clock supplying.
･INT_CLKON (bit2)
0:INT_CLKON not generated
1:INT_CLKON
This is a flag register for INT_CLKON (USB enabled to start clock supplying interrupt).
This is set to "1" when USB changed to "resume status" and enabled to start clock supplying.
6 5
R/W R/W
generated
generated
generated
generated
generated
4 3
INT_RESUMEINT_CLKSTOP INT_CLKON
R/W R/W
92CH21-182
TMP92CH21
2 1
-
R/W
0
-