Page 1 TOSHIBA Original CMOS 32-Bit Microcontroller TLCS-900/H1 Series TMP92CH21FG Semiconductor Company...
Page 2 Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, “Points of Note and Restrictions”.
Page 3 TMP92CH21 CMOS 32-bit Microcontroller TMP92CH21FG/JTMP92CH21 Outline and Device Characteristics The TMP92CH21 is a high-speed advanced 32-bit Microcontroller developed for controlling equipment which processes mass data. The TMP92CH21 has a high-performance CPU (900/H1 CPU) and various built-in I/Os. The TMP92CH21FG is housed in a 144-pin flat package. The JTMP92CH21 is a chip form product.
Page 4 TMP92CH21 (9) USB (universal serial bus) controller: 1 channel • Compliant with USB ver.1.1 • Full-speed (12 Mbps) (Low-speed is not supported.) • Endpoints spec Endpoint 0: Control 64 bytes* 1-FIFO Endpoint 1: BULK (out) 64 bytes* 2-FIFO Endpoint 2: BULK (in) 64 bytes* 2-FIFO Endpoint 3: Interrupt (in) 8 bytes* 1-FIFO •...
Page 5 VCC = 3.0 V to 3.6 V (fc max = 40 MHz) • VCC = 2.7 V to 3.6 V (fc max = 27 MHz) (26) Package: • 144-pin QFP (LQFP144-P-1616-0.40C) • 144-pin chip form is also available. For details, contact your local Toshiba sales representative. 2009-06-19 92CH21-3...
Page 6 TMP92CH21 PG0 to PG1 DVCC [4] (AN0 to AN1) DVSS [3] 900/H1 CPU AN2/MX (PG2) 10-bit AN3/MY/ (PG3) 4-channel ADTRG H-OSC AD converter AVCC, AVSS VREFH, VREFL Clock gear TEST Touch (PX, INT4) P96 screen (PY, INT5) P97 L-OSC I/F (TSI) RESET (TXD0, TXD1) PF0 Serial I/O...
Page 7 TMP92CH21 Pin Assignment and Functions The assignment of input/output pins for the TMP92CH21FG, their names and functions are as follows: Pin Assignment VREFL P67, A23 VREFH P66, A22 PG0, AN0 P65, A21 PG1, AN1 P64, A20 PG2, AN2, MX DVCC3 PG3, AN3, , MY ADTRG...
Page 8 TMP92CH21 PAD Assignment (Chip size 5.98 mm × 6.42 mm) Table 2.2.1 Pad Assignment Diagram (144-pin chip) Unit: μm Name Name Name Point Point Point Point Point Point −2852 −488 −3072 2671 DVSS2 2848 VREFL −2852 −338 −3072 2546 DVCC2 2848 VREFH −2852...
Page 9 TMP92CH21 Pin Names and Functions The following table shows the names and functions of the input/output pins Table 2.3.1 Pin Names and Functions (1/5) Number of Pin Name Function Pins D0 to D7 Data: Data bus 0 to 7 P10 to P17 Port 1: I/O port input or output specifiable in units of bits D8 to D15 Data: Data bus 8 to 15...
Page 10 TMP92CH21 Table 2.3.2 Pin Names and Functions (2/5) Number of Pin Name Function Pins Output Port80: Output port Output Chip select 0: Outputs “low” when address is within specified address area Output Port81: Output port Output Chip select 1: Outputs “low” when address is within specified address area Output Chip select for SDRAM: Outputs “0”...
Page 11 TMP92CH21 Table 2.3.3 Pin Names and Functions (3/5) Number of Pin Name Function Pins Port C0: I/O port (Schmitt-input) INT0 Input Interrupt request pin 0: Interrupt request pin with programmable level/rising/falling edge TA1OUT Output 8-bit timer 1 output: Timer 1 output Port C1: I/O port (Schmitt-input) INT1 Input...
Page 12 TMP92CH21 Table 2.3.4 Pin Names and Functions (4/5) Number of Pin Name Function Pins Output Port J0: Output port Output Row address strobe for SDRAM SDRAS Output Data enable for SRAM on pins D0 to D7 SRLLB Output Port J1: Output port Output Column address strobe for SDRAM SDCAS...
Page 13 TMP92CH21 Table 2.3.5 Pin Names and Functions (5/5) Number of Pin Name Function Pins USB-data connecting pin D+, D− Connect pull-up resistor to both pins to avoid through current when USB is not in use. Operation mode: Fix to AM1 = “0”, AM0 = “1” for 16-bit external bus starting AM0, AM1 Input Fix to AM1 = “1”, AM0 = “0”...
Page 14 TMP92CH21 Operation This section describes the basic components, functions and operation of the TMP92CH21. The TMP92CH21 contains an advanced high-speed 32-bit CPU (TLCS-900/H1 CPU) 3.1.1 CPU Outline The TLCS-900/H1 CPU is a high-speed, high-performance CPU based on the TLCS-900/L1 CPU. The TLCS-900/H1 CPU has an expanded 32-bit internal data bus to process instructions more quickly.
Page 15 TMP92CH21 3.1.2 Reset Operation When resetting the TMP92CH21, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the input low for at least 20 system clocks (16 µs at fc = 40 MHz). RESET At reset, since the clock doubler (PLL) is bypassed and the clock-gear is set to 1/16, the system clock operates at 1.25 MHz (fc = 40 MHz).
Page 16 TMP92CH21 Write Read Figure 3.1.2 TMP92CH21 Reset Timing Chart 2009-06-19 92CH21-14...
Page 17 TMP92CH21 3.1.3 Setting of AM0 and AM1 Set AM1 and AM0 pins as shown in Table 3.1.2 according to system usage. Table 3.1.2 Operation Mode Setup Table Mode Setup Input Pin Operation Mode RESET 16-bit external bus starting (MULTI 16 mode) 32-bit external bus starting (MULTI 32 mode) Boot (32-bit internal MROM) starting...
Page 18 TMP92CH21 Memory Map Figure 3.2.1 is a memory map of the TMP92CH21. 000000H Internal I/O Direct area (n) (8 Kbytes) 000100H 001D00H 002000H 64-Kbyte area Internal RAM (nn) (16 Kbytes) 006000H 010000H 3FE000H Boot (Internal MROM) (Note 1) (8 Kbytes) 400000H External memory F00000H...
Page 19 TMP92CH21 Clock Function and Stand-by Function The TMP92CH21 contains (1) clock gear, (2) clock doubler (PLL), (3) stand-by controller and (4) noise reduction circuits. They are used for low power, low noise systems. This chapter is organized as follows: 3.3.1 Block diagram of system clock 3.3.2 3.3.3...
Page 20 TMP92CH21 The clock operating modes are as follows: (a) single clock mode (X1, X2 pins only), (b) dual clock mode (X1, X2, XT1 and XT2 pins) and (c) triple clock mode (X1, X2, XT1 and XT2 pins and PLL). Figure 3.3.1 shows a transition figure. Reset /32) OSCH...
Page 21 TMP92CH21 3.3.1 Block Diagram of System Clock SYSCR0<WUEF> SYSCR2<WUPTM1:0> φT Warm-up timer (High/low-frequency oscillator) φT0 Lock up timer ÷4 ÷8 (PLL) SYSCR0<XTEN > PLLCR1<PLLON>, PLLCR0<LUPFG> Low-frequency ÷2 oscillator fc/2 ÷2 × 4 OSCH fc/4 fc/8 SYSCR1<SYSCK> SYSCR0<XEN > Selector fc/16 Clock doubler (PLL) ÷2...
Page 22 TMP92CH21 3.3.2 Bit symbol XTEN WUEF SYSCR0 (10E0H) Read/Write Reset state Function High- Low- Warm-up frequency frequency timer oscillator oscillator 0: Write (fc) (fs) don’t care 0: Stop 0: Stop 1: Write 1: Oscillation 1: Oscillation start timer 0: Read warm-up 1: Read do not end...
Page 23 TMP92CH21 Bit symbol PROTECT EXTIN EMCCR0 DRVOSCH DRVOSCL (10E3H) Read/Write Reset state Function Protect flag 1: External fc oscillator fs oscillator clock driver ability driver ability 0: OFF 1: Normal 1: Normal 1: ON 0: Weak 0: Weak EMCCR1 Bit symbol (10E4H) Read/Write Reset state...
Page 24 TMP92CH21 Bit symbol FCSEL LUPFG PLLCR0 (10E8H) Read/Write Reset state Function Select fc Lock up clock timer 0: f status flag OSCH 1: f 0: Not end 1: End Note: Ensure that the logic of PLLCR0<LUPFG> is different from 900/L1’s DFM. PLLCR1 Bit symbol PLLON...
Page 25 TMP92CH21 3.3.3 System Clock Controller The system clock controller generates the system clock signal (f ) for the CPU core and internal I/O. It contains two oscillation circuits and a clock gear circuit for high-frequency (fc) operation. The register SYSCR1<SYSCK> changes the system clock to either fc or fs, SYSCR0<XEN>...
Page 26 TMP92CH21 Example 1: Setting the clock Changing from high-frequency (fc) to low-frequency (fs). SYSCR0 10E0H SYSCR1 10E1H SYSCR2 10E2H (SYSCR2), 0 X 1 1 − − X X B ; Sets warm-up time to 2 /fs. 6, (SYSCR0) Enables low-frequency oscillation. 2, (SYSCR0) Clears and starts warm-up timer.
Page 27 TMP92CH21 Example 2: Setting the clock Changing from low-frequency (fs) to high-frequency (fc). SYSCR0 10E0H SYSCR1 10E1H SYSCR2 10E2H (SYSCR2), 0 X 1 0 − − X X B ; Sets warm-up time to 2 /fc. 7, (SYSCR0) Enables high-frequency oscillation. 2, (SYSCR0) Clears and starts warm-up timer.
Page 28 TMP92CH21 (2) Clock gear controller is set according to the contents of the clock gear select register SYSCR1<GEAR2:0> to either fc, fc/2, fc/4, fc/8 or fc/16. Using the clock gear to select a lower value of f reduces power consumption. Example 3: Changing to a high-frequency gear SYSCR1 10E1H...
Page 29 TMP92CH21 3.3.4 Clock Doubler (PLL) PLL outputs the f clock signal, which is four times as fast as f OSCH low-speed-frequency oscillator can be used, even though the internal clock is high-frequency. A reset initializes PLL to stop status, so setting to PLLCR0, PLLCR1 register is needed before use.
Page 30 TMP92CH21 Example 2: PLL stopping PLLCR0 10E8H PLLCR1 10E9H (PLLCR0), X0XXXXXXB Changes fc from 40 MHz to10 MHz. (PLLCR1), 0XXXXXXXB Stop PLL. X: Don’t care <FCSEL> <PLLON> PLL output: f System clock f Changes from 40 MHz to 10 MHz Stops PLL operation 2009-06-19 92CH21-28...
Page 31 TMP92CH21 Limitations on the use of PLL It is not possible to execute PLL enable/disable control in the SLOW mode (fs) (writing to PLLCR0 and PLLCR1). PLL should be controlled in the NORMAL mode. 2. When stopping PLL operation during PLL use, execute the following settings in the same order.
Page 32 TMP92CH21 (2) Change/stop control (OK) PLL use mode (f ) → High-frequency oscillator operation mode (f ) → OSCH PLL Stop → Low-frequency oscillator operation mode (fs) → High-frequency oscillator stop − 0 − − − − − − B ; (PLLCR0), Change the system clock f to f...
Page 33 TMP92CH21 3.3.5 Noise Reduction Circuits Noise reduction circuits are built-in, allowing implementation of the following features. (1) Reduced drivability for high-frequency oscillator (2) Reduced drivability for low-frequency oscillator (3) Single drive for high-frequency oscillator (4) SFR protection of register contents (1) Reduced drivability for high-frequency oscillator (Purpose) Reduces noise and power for oscillator when a resonator is used.
Page 34 TMP92CH21 (2) Reduced drivability for low-frequency oscillator (Purpose) Reduces noise and power for oscillator when a resonator is used. (Block diagram) XT1 pin Enable oscillation Resonator EMCCR0<DRVOSCL> XT2 pin (Setting method) The drive ability of the oscillator is reduced by writing 0 to the EMCCR0<DRVOSCL>...
Page 35 TMP92CH21 (4) Runaway prevention using SFR protection register (Purpose) Prevention of program runaway caused by introduction of noise. Write operations to a specified SFR are prohibited so that the program is protected from runaway caused by stopping of the clock or by changes to the memory control register (memory controller, MMU) which prevent fetch operations.
Page 36 TMP92CH21 3.3.6 Stand-by Controller (1) HALT modes and port drive register When the HALT instruction is executed, the operating mode switches to IDLE2, IDLE1 or STOP mode, depending on the contents of the SYSCR2<HALTM1:0> register and each pin-status is set according to the PxDR register, as shown below: PxDR Bit symbol Px7D...
Page 37 TMP92CH21 The operation of each of the different HALT modes is described in Table 3.3.4. Table 3.3.4 I/O Operation during HALT Modes HALT Mode IDLE2 IDLE1 STOP SYSCR2<HALTM1:0> Stop I/O ports Depend on PxDR register setting TMRA, TMRB Available to select operation block AD converter Block...
Page 38 TMP92CH21 Table 3.3.5 Source of Halt State Clearance and Halt Clearance Operation Interrupt Enabled Interrupt Disabled Status of Received Interrupt Interrupt level) ≥ (Interrupt mask) Interrupt level) < (Interrupt mask) HALT Mode IDLE2 IDLE1 STOP IDLE2 IDLE1 STOP ♦ × ×...
Page 39 TMP92CH21 (3) Operation IDLE2 mode In IDLE2 mode only specific internal I/O operations, as designated by the IDLE2 setting register, can take place. Instruction execution by the CPU stops. Figure 3.3.7 illustrates an example of the timing for clearance of the IDLE2 mode halt state by an interrupt.
Page 40 TMP92CH21 STOP mode When STOP mode is selected, all internal circuits stop, including the internal oscillator. After STOP mode has been cleared system clock output starts when the warm-up time has elapsed, in order to allow oscillation to stabilize. Figure 3.3.9 illustrates the timing for clearance of the STOP mode halt state by an interrupt.
Page 41 TMP92CH21 Table 3.3.7 Input Buffer State Table Input Buffer State In HALT mode (IDLE1/2/STOP) When the CPU is Input operating <PxDR> = 1 <PxDR> = 0 Port Name Function During Name When used When used When used When used When used When used Reset Function pin...
Page 42 TMP92CH21 Table 3.3.8 Output Buffer State Table (1/2) Output Buffer State In HALT mode (IDLE1/2/STOP) When the CPU is Output operating <PxDR>=1 <PxDR>=0 Port Name Function During When used When used When used When used When used When used Name Reset Function pin Output pin...
Page 43 TMP92CH21 Table 3.3.9 Output Buffer State Table (2/2) Output Buffer State In HALT mode (IDLE1/2/STOP) When the CPU is Output operating Port <PxDR>=1 <PxDR>=0 Function During Name When used When used When used When used When used When used Name Reset Function pin Output pin...
Page 44 TMP92CH21 Interrupts Interrupts are controlled by the CPU Interrupt mask register <IFF2:0> (bits12 to 14 of the status register) and by the built-in interrupt controller. The TMP92CH21 has a total of 50 interrupts divided into the following five types: Interrupts generated by CPU: 9 sources Software interrupts: 8 sources Illegal instruction interrupt: 1 source Internal interrupts: 34 sources...
Page 45 TMP92CH21 Micro DMA soft Interrupt processing start request Interrupt specified by micro DMA start vector ? Clear interrupt request flag Data transfer by micro Interrupt vector calue “V” read interrupt request F/F clear Micro DMA General-purpose processing interrupt COUNT ← COUNT − 1 PUSH processing PUSH...
Page 46 TMP92CH21 3.4.1 General-purpose Interrupt Processing When the CPU accepts an interrupt, it usually performs the following sequence of operations. However, in the case of software interrupts and illegal instruction interrupts generated by the CPU, the CPU skips steps (1) and (3), and executes only steps (2), (4) and (5).
Page 47 TMP92CH21 Table 3.4.1 TMP92CH21 Interrupt Vectors and Micro DMA Start Vectors Micro Interrupt Source and Source of Default Vector Address Refer Type DMA Start Priority Value to Vector Micro DMA Request Vector Reset or [SWI0] instruction 0000H FFFF00H [SWI1] instruction 0004H FFFF04H Illegal instruction or [SWI2] instruction...
Page 48 TMP92CH21 Micro Interrupt Source and Source of Default Vector Address Refer Type DMA Start Priority Value to Vector Micro DMA Request Vector (Reserved) 00C8H FFFFC8H INTAD: AD conversion end 00CCH FFFFCCH INTTC0: Micro DMA end (Channel 0) 00D0H FFFFD0H INTTC1: Micro DMA end (Channel 1) 00D4H FFFFD4H INTTC2: Micro DMA end (Channel 2)
Page 49 TMP92CH21 3.4.2 Micro DMA Processing In addition to general purpose interrupt processing, the TMP92CH21 also includes a micro DMA function. Micro DMA processing for interrupt requests set by micro DMA is performed at the highest priority level for maskable interrupts (level 6), regardless of the priority level of the interrupt source.
Page 50 TMP92CH21 Although the control registers used for setting the transfer source and transfer destination addresses are 32 bits wide, this type of register can only output 24-bit addresses. Accordingly, micro DMA can only access 16 Mbytes (the upper eight bits of a 32-bit address are not valid).
Page 51 TMP92CH21 (2) Soft start function The TMP92CH21 can initiate micro DMA either with an interrupt or by using the micro DMA soft start function, in which micro DMA is initiated by a write cycle which writes to the register DMAR. Writing 1 to any bit of the register DMAR causes micro DMA to be performed once.
Page 52 TMP92CH21 (4) Detailed description of the transfer mode register Mode DMAM0 to DMAM7 Execution DMAMn[4:0] Mode Description State Number 0 0 0 z z Destination INC mode (DMADn+) ← (DMASn) DMACn ← DMACn − 1 5 states If DMACn = 0 then INTTCn 0 0 1 z z Destination DEC mode (DMADn−) ←...
Page 53 TMP92CH21 3.4.3 Interrupt Controller Operation The block diagram in Figure 3.4.3 shows the interrupt circuits. The left hand side of the diagram shows the interrupt controller circuit. The right hand side shows the CPU interrupt request signal circuit and the halt release circuit. For each of the 52 interrupts channels there is an interrupt request flag (consisting of a flip-flop), an interrupt priority setting register and a micro DMA start vector register.
Page 54 TMP92CH21 Figure 3.4.3 Block Diagram of Interrupt Controller 2009-06-19 92CH21-52...
Page 55 TMP92CH21 (1) Interrupt level setting registers Symbol Name Address INTAD INT0 INT0 & IADC IADM2 IADM1 IADM0 I0M2 I0M1 I0M0 INTE0AD INTAD enable INT2 INT1 INT1 & I2M2 I2M1 I2M0 I1M2 I1M1 I1M0 INTE12 INT2 enable INT4 INT3 INT3 & I4M2 I4M1 I4M0...
Page 56 TMP92CH21 Symbol Name Address − INTALM4 − − − − INTALM4 IA4C IA4M2 IA4M1 IA4M0 INTEALM4 enable Note: Always write 0 − INTRTC − − − − INTRTC IRM2 IRM1 IRM0 INTERTC enable Note: Always write 0 − INTKEY − −...
Page 57 TMP92CH21 Symbol Name Address INTTC1 (DMA1) INTTC0 (DMA0) INTTC0 ITC1C ITC1M2 ITC1M1 ITC1M0 ITC0C ITC0M2 ITC0M1 ITC0M0 & INTETC01 INTTC1 enable INTTC3 (DMA3) INTTC2 (DMA2) INTTC2 ITC3C ITC3M2 ITC3M1 ITC3M0 ITC2C ITC2M2 ITC2M1 ITC2M0 & INTETC23 INTTC3 enable INTTC5 (DMA5) INTTC4 (DMA4) INTTC4 ITC5C...
Page 58 TMP92CH21 (2) External interrupt control Symbol Name Address − I5EDGE I4EDGE I3EDGE I2EDGE I1EDGE I0EDGE I0LE Interrupt INT5EDGE INT4EDGE INT3EDGE INT2EDGE INT1EDGE INT0EDGE 0: INT0 Always input IIMC (Prohibit edge write “0” mode 0: Rising 0: Rising 0: Rising 0: Rising 0: Rising 0: Rising RMW)
Page 59 TMP92CH21 (3) SIO receive interrupt control Symbol Name Address − IR1LE IR0LE Always 0: INTRX1 0: INTRX0 interrupt SIMC (Prohibit write “0” edge edge mode RMW) mode mode (Note) control 1: INTRX1 1: INTRX0 level level mode mode Note: When using the micro DMA transfer end interrupt, always write “1”. INTRX1 level enable Edge detect INTRX1 “H”...
Page 60 TMP92CH21 (4) Interrupt request flag clear register The interrupt request flag is cleared by writing the appropriate micro DMA start vector, as given in Table 3.4.1, to the register INTCLR. For example, to clear the interrupt flag INT0, perform the following register operation after execution of the DI instruction.
Page 61 TMP92CH21 Symbol Name Address DMA0V5 DMA0V4 DMA0V3 DMA0V2 DMA0V1 DMA0V0 DMA0 DMA0V start 100H vector DMA0 start vector DMA1V5 DMA1V4 DMA1V3 DMA1V2 DMA1V1 DMA1V0 DMA1 DMA1V start 101H vector DMA1 start vector DMA2V5 DMA2V4 DMA2V3 DMA2V2 DMA2V1 DMA2V0 DMA2 DMA2V start 102H vector...
Page 62 TMP92CH21 (6) Specification of a micro DMA burst Specifying the micro DMA burst function causes micro DMA transfer, once started, to continue until the value in the transfer counter register reaches zero. Setting any of the bits in the register DMAB which correspond to a micro DMA channel (as shown below) to 1 specifies that any micro DMA transfer on that channel will be a burst transfer.
Page 63 TMP92CH21 (7) Notes The instruction execution unit and the bus interface unit in this CPU operate independently. Therefore, immediately before an interrupt is generated, if the CPU fetches an instruction which clears the corresponding interrupt request flag, the CPU may execute this instruction in between accepting the interrupt and reading the interrupt vector.
Page 64 TMP92CH21 Function of Ports The TMP92CH21 I/O port pins are shown in Table 3.5.1 and Table 3.5.2. In addition to functioning as general-purpose I/O ports, these pins are also used by the internal CPU and I/O functions. Table 3.5.3 to Table 3.5.5 list the I/O registers and their specifications. Table 3.5.1 Port Functions (1/2) R: PD = with programmable pull-down resistor, U = with pull-up resistor) Number...
Page 65 TMP92CH21 Table 3.5.2 Port Functions (2/2) R: PD = with programmable pull-down resistor, U = with pull-up resistor) Number Port Name Pin Name I/O Setting Pin Name for Built-in Function of Pins − Port G PG0 to PG1 Input (Fixed) AN0 to AN1 −...
Page 66 TMP92CH21 Table 3.5.3 I/O Registers and Specifications (1/3) X: Don’t care I/O Register Port Pin Name Specification PnCR PnFC PnFC2 Port 1 P10 to P17 Input port None Output port D8 to D15 bus Port 2 P20 to P27 Input port Output port D16 to D23 bus KO0 to KO7...
Page 67 TMP92CH21 Table 3.5.4 I/O Registers and Specifications (2/3) X: Don’t care I/O Register Port Pin Name Specification PnCR PnFC PnFC2 Port 9 P90 to P94, Input port P96 to P97 P90 to P94 Output port TXD0 output I2SCKO output TXD0 output (Open drain) RXD0 input I2SDO output SCLK0 output...
Page 68 TMP92CH21 Table 3.5.5 I/O Registers and Specifications (3/3) X: Don’t care I/O Register Port Pin Name Specification PnCR PnFC PnFC2 Port G PG0 to PG3 Input port AN0 to AN3 input None None None input ADTRG MX output MY output Port J PJ0 to PJ7 Output port...
Page 69 TMP92CH21 3.5.1 Port 1 (P10 to P17) Port 1 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P1CR and function register P1FC. In addition to functioning as a general-purpose I/O port, port1 can also function as a data bus (D8 to D15).
Page 70 TMP92CH21 Port 1 register Bit symbol (0004H) Read/Write Reset State Data from external port (Output latch register is cleared to “0”) Port 1 Control register P1CR Bit symbol P17C P16C P15C P14C P13C P12C P11C P10C (0006H) Read/Write Reset State Function 0: Input 1: Output Port 1 Function register...
Page 71 TMP92CH21 3.5.2 Port 2 (P20 to P27) Port 2 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P2CR and function register P2FC. In addition to functioning as a general-purpose I/O port, port 2 can also function either as a data bus (D16 to D23) or keyboard interface pin KO0 to KO7 which can be set to open-drain output buffer.
Page 72 TMP92CH21 Port 2 register Bit symbol (0008H) Read/Write Reset State Data from external port (Output latch register is cleared to “0”) Port 2 Control register P2CR Bit symbol P27C P26C P25C P24C P23C P22C P21C P20C (000AH) Read/Write Reset State Function 0: Input 1: Output Port 2 Function register...
Page 73 TMP92CH21 3.5.3 Port 3 (P30 to P37) Port 3 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P3CR and function register P3FC. In addition to functioning as a general-purpose I/O port, port 3 can also function as a data bus (D24 to D31).
Page 74 TMP92CH21 Port 3 register Bit symbol (000CH) Read/Write Reset State Data from external port (Output latch register is cleared to “0”) Port 3 Control register P3CR Bit symbol P37C P36C P35C P34C P33C P32C P31C P30C (000EH) Read/Write Reset State Function 0: Input 1: Output Port 3 Function register...
Page 75 TMP92CH21 3.5.4 Port 4 (P40 to P47) Port 4 is an 8-bit general-purpose output port. In addition to functioning as a general-purpose output port, port 4 can also function as an address bus (A0 to A7). Function Setting after Reset is Released Don’t use this setting Address bus (A0 to A7) Address bus (A0 to A7)
Page 76 TMP92CH21 Port 4 register Bit symbol (0010H) Read/Write Reset State Port 4 Function register P4FC Bit symbol P47F P46F P45F P44F P43F P42F P41F P40F (0013H) Read/Write Reset State Note 2 Function 0: Port 1: Address bus (A0 to A7) Port 4 Drive register P4DR Bit symbol...
Page 77 TMP92CH21 3.5.5 Port 5 (P50 to P57) Port 5 is an 8-bit general-purpose output port. In addition to functioning as a general-purpose I/O port, port 5 can also function as an address bus (A8 to A15). Function Setting after Reset is Released Don’t use this setting Address bus (A8 to A15) Address bus (A8 to A15)
Page 78 TMP92CH21 Port 5 register Bit symbol (0014H) Read/Write Reset State Port 5 Function register P5FC Bit symbol P57F P56F P55F P54F P53F P52F P51F P50F (0017H) Read/Write Reset State Note 2 Function 0: Port 1: Address bus (A8 to A15) Port 5 Drive register P5DR Bit symbol...
Page 79 TMP92CH21 3.5.6 Port 6 (P60 to P67) Port 6 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P6CR and function register P6FC. In addition to functioning as a general-purpose I/O port, port 6 can also function as an address bus (A16 to A23).
Page 80 TMP92CH21 Port 6 register Bit symbol (0018H) Read/Write Reset State Data from external port (Output latch register is cleared to “0”) Port 6 Control register P6CR Bit symbol P67C P66C P65C P64C P63C P62C P61C P60C (001AH) Read/Write Reset State Function 0: Input 1: Output Port 6 Function register...
Page 81 TMP92CH21 3.5.7 Port 7 (P70 to P76) Port 7 is a 7-bit general-purpose I/O port (P70, P73 and P74 are used for output only). Bits can be individually set as either inputs or outputs by control register P7CR and function register P7FC. In addition to functioning as a general-purpose I/O port, P70 to P76 pins can also function as interface pins for external memory.
Page 82 TMP92CH21 P7CR register P7FC register P7 register P75 (R/ , NDR/ B ) Selector Port read data NDR/ B P7CR register P7FC register P7 register P76 ( WAIT Port read data WAIT Figure 3.5.14 Port 7 2009-06-19 92CH21-80...
Page 83 TMP92CH21 Port 7 register Bit symbol (001CH) Read/Write Data from external port Data from external port Reset State (Output latch register is (Output latch register is set to “1”) set to “1”) Port 7 Control register P7CR Bit symbol P76C P75C P72C P71C...
Page 84 TMP92CH21 3.5.8 Port 8 (P80 to P87) Ports 80 to 87 are 8-bit output ports. Resetting sets the output latch of P82 to “0” and the output latches of P80 to P81, P83 to P87 to “1”. Port 8 can also be set to function as an interface pin for external memory using function register P8FC.
Page 85 TMP92CH21 Port 8 Register Bit symbol (0020H) Read/Write Reset State 0/1 Note2 Port 8 Function Register P8FC Bit symbol P87F P86F P85F P84F P83F P82F P81F P80F (0023H) Read/Write Reset State Function Refer to Refer to Refer to Port Port Port Port Port...
Page 86 TMP92CH21 3.5.9 Port 9 (P90 to P97) P90 to P94 are 5-bit general-purpose I/O ports. I/O can be set on a bit basis using the control register. Resetting sets P90 to P94 to input port and all bits of output latch to“1”. P95 is 1-bit general-purpose output port and P96 to P97 are 2-bit general-purpose input ports.
Page 87 TMP92CH21 Reset Direction control P9CR write Function control P9FC write Output latch P91 (RXD0, I2SDO) P92 (SCLK0, , I2SWS) Selector P9 write I2SDO output SCLK0,I2SWS output Selector P9 read (to Port F1) P91RXD0 input (to Port F2) P92SCLK0 input Figure 3.5.19 P91 and P92 (2) P93 (LGOE0), P94 (LGOE1) Reset Direction control...
Page 88 TMP92CH21 (3) P95 (CLK32KO, LGOE2) Reset Direction control P9CR write Function control P9FC write P95 (LGOE2, CLK32KO) Output latch Selector P9 write LGOE2 P9 read Figure 3.5.21 Port 95 (4) P96 (INT4, PX), P97 (INT5, PY) Reset AVCC Function control TSICR0<PXEN>...
Page 89 TMP92CH21 Port 9 Register Bit symbol (0024H) Read/Write Reset State Data from external port Data from external port (Output latch register is set to “1”) Port 9 Function Register P9FC Bit symbol P95C P94C P93C P92C P91C P90C (0026H) Read/Write Reset State Function Refer to following table...
Page 90 TMP92CH21 3.5.10 Port A (PA0 to PA7) Ports A0 to A7 are 8-bit input ports with pull-up resistor. In addition to functioning as general-purpose I/O ports, ports A0 to A7 can also, as a keyboard interface, operate a key-on wakeup function. The various functions can each be enabled by writing a “1” to the corresponding bit of the port A function register (PAFC).
Page 91 TMP92CH21 Port A Register Bit symbol (0028H) Read/Write Reset State Data from external port Port A Function Register PAFC Bit symbol PA7F PA6F PA5F PA4F PA3F PA2F PA1F PA0F (002BH) Read/Write Reset State Function 0: Key input disable 1: Key input enable Port A Control Register PACR Bit symbol...
Page 92 TMP92CH21 3.5.11 Port C (PC0 to PC3, PC6 to PC7) PC0 to PC3, PC6 and PC7 are 6-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets port C to an input port. In addition to functioning as a general-purpose I/O port, port C can also function as an output pin for timers (TA1OUT, TA3OUT and TB0OUT0), input pin for external interruption (INT0 to INT3), output pin for memory ( ), output pin for key (KO8) and...
Page 93 TMP92CH21 (2) PC1 (INT1, TA3OUT), PC2 (INT2, TB0OUT0), PC3 (INT3, TB0OUT1) Reset Direction control PCCR write Function control PCFC write PC1 (INT1, TA3OUT) Output latch Selector PC2 (INT2, TB0OUT0) PC3 (INT3) PC write TA3OUT TB0OUT0 Selector PC read INT1 Rising/falling INT3 edge detection IIMC<I1EDGE,...
Page 94 TMP92CH21 (3) PC6 (KO8, LDIV) Reset Direction control PCCR write Function control PCFC write PC6 (KO8, LDIV) Output latch Selector Open drain possible PC write LDIV Selector PC read Figure 3.5.28 Port (4) PC7 ( , LCP1) CSZF Reset Direction control PCCR write Funtcion control PC7 (...
Page 95 TMP92CH21 Port C Register Bit symbol (0030H) Read/Write Reset State Data from external port Data from external port (Output latch register is (Output latch register is set to “1”) set to “1”) Port C Control Register PCCR Bit symbol PC7C PC6C PC3C PC2C...
Page 96 TMP92CH21 3.5.12 Port F (PF0 to PF2, PF7) Ports F0 to F2 are 3-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets PF0 to PF2 to be input ports. It also sets all bits of the output latch register to “1”.
Page 97 TMP92CH21 Reset Direction control PFCR write PF1 (RXD0,RXD1) Output latch PF write Selector read PFFC<PF1F> RXD0 Selector P91RXD0 input RXD1 Figure 3.5.32 Port F1 Reset Direction control PFCR write PF2 (SCLK0, Output latch Selector SCLK0 output SCLK1, SCLK1 output PF write Function control PFFC write Selector...
Page 98 TMP92CH21 Reset Function control PFFC write Output latch PF7 (SDCLK) Selector SDCLK PF write PF read Figure 3.5.34 Port F7 2009-06-19 92CH21-96...
Page 99 TMP92CH21 Port F Register Bit symbol (003CH) Read/Write Reset State External data (Output latch register is set to “1”) Port F Control Register PFCR Bit symbol PF2C PF1C PF0C (003EH) Read/Write Reset State Function Refer to following table Port F Functon Register PFFC Bit symbol PF7F...
Page 100 TMP92CH21 3.5.13 Port G (PG0 to PG3) PG0 to PG3 are 4-bit input ports and can also be used as the analog input pins for the internal AD converter. PG3 can also be used as the ADTRG pin for the AD converter. PG2 and PG3 can also be used as the MX and MY pins for a touch screen interface.
Page 101 TMP92CH21 3.5.14 Port J (PJ0 to PJ7) PJ0 to PJ4 and PJ7 are 6-bit output ports. Resetting sets the output latch PJ to “1”, and they output “1”. PJ5 to PJ6 are 2-bit I/O ports. In addition to functioning as a port, port J also functions as output pins for SDRAM , SDLLDQM, SDLUDQM, SDULDQM, SDUUDQM and SDCKE), SDRAS SDCAS...
Page 102 TMP92CH21 Port J Register Bit symbol (004CH) Read/Write Reset State Data from external port (Output latch register is set to “1”) Port J Control Register PJCR Bit symbol PJ6C PJ5C (004EH) Read/Write Reset State Function 0: Input 1: Output Port J Function Register PJFC Bit symbol PJ7F...
Page 103 TMP92CH21 3.5.15 Port K (PK0 to PK3) Port K is a 4-bit output port. Resetting sets the output latch PK to “0”, and PK0 to PK3 pins output “0”. In addition to functioning as an output port, port K also functions as output pins for an LCD controller (LCP0, LLP, LFR and LBCD).
Page 104 TMP92CH21 3.5.16 Port L (PL0 to PL7) PL0 to PL3 are 4-bit output ports. Resetting sets the output latch PL to “0”, and PL0 to PL3 pins output “0”. PL4 to PL7 are 4-bit general-purpose I/O ports. Each bit can be set individually for input or output using the control register PLCR.
Page 105 TMP92CH21 Port L Register Bit symbol (0054H) Read/Write Reset State Data from external port (Output latch register is cleared to “0”) Port L Control Register PLCR Bit symbol PL7C PL6C PL5C PL4C (0056H) Read/Write Reset State Function 0: Input 1: Output Port L Function Register PLFC Bit symbol...
Page 106 TMP92CH21 3.5.17 Port M (PM1 to PM2) PM1 and PM2 are 2-bit output ports. Resetting sets the output latch PM to “1”, and PM1 and PM2 pins output “1”. In addition to functioning as a port, port M also functions as output pins for the RTC alarm ( ), and as the output pin for the melody/alarm generator (MLDALM, ALARM...
Page 107 TMP92CH21 Port M Register Bit symbol (0058H) Read/Write Reset State Port M Function Register PMFC Bit symbol PM2F PM1F (005BH) Read/Write Reset State Function 0: Port : Port 1: MLDALM ALARM <PM2> = “1” output MLDALM <PM2> = “0” Port M Drive Register PMDR Bit symbol PM2D...
Page 108 TMP92CH21 Memory Controller 3.6.1 Functions The TMP92CH21 has a memory controller with a variable 4-block address area that controls as follows. (1) 4-block address area support Specifies a start address and a block size for the 4-block address area (block 0 to 3). •...
Page 109 TMP92CH21 Table 3.6.1 Control Register B0CSL Bit symbol B0WW2 B0WW1 B0WW0 B0WR2 B0WR1 B0WR0 (0140H) Read/Write Reset State − − B0CSH Bit symbol B0REC B0OM1 B0OM0 B0BUS1 B0BUS0 (0141H) Read/Write Reset State 0 (Note) 0 (Note) MAMR0 Bit symbol M0V20 M0V19 M0V18 M0V17...
Page 110 TMP92CH21 Table 3.6.2 Control Register BEXCSH Bit symbol BEXOM1 BEXOM0 BEXBUS1 BEXBUS0 (0159H) Read/Write Reset State BEXCSL Bit symbol BEXWW2 BEXWW1 BEXWW0 BEXWR2 BEXWR1 BEXWR0 (0158H) Read/Write Reset State PMEMCR Bit symbol OPGE OPWR1 OPWR0 (0166H) Read/Write Reset State BROMCR Bit symbol ROMLESS VACE...
Page 111 TMP92CH21 3.6.3 Basic Functions and Register Setting This section describes the setting of the block address area, the connecting memory and the number of waits out of the memory controller’s functions. (1) Block address area specification The block address area is specified by two registers. The memory start address register (MSARn) sets the start address of the block address areas.
Page 112 TMP92CH21 (iii) Example of register setting To set the block address area 64 Kbytes from address 110000H, set the register as follows. MSAR1 Register Bit symbol M1S23 M1S22 M1S21 M1S20 M1S19 M1S18 M1S17 M1S16 Specified value M1S23 to M1S16 bits of the memory start address register MSAR1 correspond with address A23 to A16.
Page 113 TMP92CH21 (2) Connection memory specification Setting the <BnOM1:0> bit of the control register (BnCSH) specifies the memory type that is connected with the block address areas. The interface signal is outputted according to the set memory as follows. <BnOM1: 0> Bit (BnCSH Register) <BnOM1>...
Page 114 TMP92CH21 Operand Start Memory Data Size CPU Data Operand Data CPU Address Size (bit) Address (bit) D31 to D24 D23 to D16 D15 to D8 D7 to D0 4n + 0 4n + 0 8/16/32 xxxxx xxxxx xxxxx b7 to b0 4n + 1 4n + 1 xxxxx...
Page 115 TMP92CH21 (4) Wait control = 20 The external bus cycle completes a wait of at least two states (100 ns at f MHz). Setting the <BnWW2:0> and <BnWR2:0> of BnCSL specifies the number of waits in the write cycle and the read cycle. <BnWW2:0> is set using the same method as <BnWR2:0>.
Page 116 TMP92CH21 (5) Recovery (Data hold) cycle control Some memory is defined by AC specification about data hold time by read cycle. Therefore, a data conflict problem may occur. To avoid this problem, 1-dummy cycle can be inserted after CSm-block access cycle by setting “1” to BmCSH<BmREC>...
Page 117 TMP92CH21 (6) Basic bus timing (a) External read/write cycle (0 waits) SDCLK (20 MHz) A23 to A0 SRxxB Read D31 to D0 Input SRWR SRxxB Write WRxx D31 to D0 Output (b) External read/write cycle (1 wait) SDCLK (20 MHz) A23 to A0 SRxxB Read...
Page 118 TMP92CH21 (c) External read/write cycle (0 waits at pin input mode) WAIT SDCLK (20 MHz) A23 to A0 SRxxB Read D31 to D0 Input SRWR SRxxB Write WRxx D31 to D0 Output WAIT Sampling (d) External read/write cycle (n waits at pin input mode) WAIT SDCLK...
Page 119 TMP92CH21 Example of wait input cycle (5 waits) WAIT SDCLK SRWR SDCLK (20 MHz) FF_RES FF0_D FF0_Q FF1_Q FF2_Q FF3_Q WAIT 2009-06-19 92CH21-117...
Page 120 TMP92CH21 (7) Connecting external memory Figure 3.6.1 shows an example of how to connect an external 16-bit SRAM and 16-bit NOR flash to the TMP92CH21. TMP92CH21 16-bit SRAM SRLLB SRLUB SRWR D [15:0] I/O [16:1] Not connect 16-bit NOR flash DQ [15:0] Figure 3.6.1 Example of External 16-Bit SRAM and NOR Flash Connection 2009-06-19...
Page 121 TMP92CH21 3.6.4 ROM Control (Page mode) This section describes ROM page mode accessing and how to set registers. ROM page mode is set by the page ROM control register. (1) Operation and how to set the registers The TMP92CH21 supports ROM access of the page mode. ROM access of the page mode is specified only in block address area 2.
Page 122 TMP92CH21 3.6.5 Internal Boot ROM Control This section describes the built-in boot ROM. For the specification of S/W in boot ROM, refer to 3.20 boot ROM sections. (1) BOOT mode BOOT mode is started by following AM1 and AM0 pins condition with reset. Start mode Don’t use this setting Start with 16-bit data bus...
Page 123 TMP92CH21 (4) Bypassing boot ROM After boot sequence in BOOT mode, an application system program may continue to run without reset asserting. In this case, an external memory which is mapped to address 3FE000H to 3FFFFFH cannot be accessed because the boot ROM is assigned. solve this, internal...
Page 124 TMP92CH21 3.6.6 Cautions (1) Note on timing between If the parasitic capacitance of the (Read signal) is greater than that of the (Chip select signal), it is possible that an unintended read cycle occurs due to a delay in the read signal. Such an unintended read cycle may cause a problem, as in the case of (a) in Figure 3.6.3.
Page 125 TMP92CH21 (2) Note on NAND flash area setting Figure 3.6.5 shows a memory map for a NAND flash and RAM built-in LCD driver. Ssince it is recommended that CS3 area be assigned to the address 000000H to 3FFFFFH, the following explanation is given. In this case, the NAND flash and RAM built-in LCD driver overlap with CS3 area.
Page 126 TMP92CH21 (3) The cautions at the time of the functional change of a A chip select signal output has the case of a combination terminal with a general-purpose port function. In this case, an output latch register and a function control register are initialized by the reset action, and an object terminal is initialized by the port output (“1”...
Page 127 TMP92CH21 8-Bit Timers (TMRA) The TMP92CH21 features 4 built-in 8-bit timers (TMRA0-TMRA3). These timers are paired into two modules: TMRA01 and TMRA23. Each module consists of two channels and can operate in any of the following four operating modes. • 8-bit interval timer mode •...
Page 128 TMP92CH21 3.7.1 Block Diagrams Figure 3.7.1 TMRA01 Block Diagram 2009-06-19 92CH21-126...
Page 129 TMP92CH21 Figure 3.7.2 TMRA23 Block Diagram 2009-06-19 92CH21-127...
Page 130 TMP92CH21 3.7.2 Operation of Each Circuit (1) Prescalers A 9-bit prescaler generates the input clock to TMRA01. The clock φT0 is divided into 8 by the CPU clock f and input to this prescaler. The prescaler operation can be controlled using TA01RUN<TA01PRUN> in the timer control register.
Page 131 TMP92CH21 (3) Timer registers (TA0REG and TA1REG) These are 8-bit registers, which can be used to set a time interval. When the value set in the timer register TA0REG or TA1REG matches the value in the corresponding up counter, the comparator match detect signal goes Active. If the value set in the timer register is 00H, the signal goes Active when the up counter overflows.
Page 132 TMP92CH21 (4) Comparator (CP0) The comparator compares the value in an up counter with the value set in a timer register. If they match, the up counter is cleared to “0” and an interrupt signal (INTTA0 or INTTA1) is generated. If timer flip-flop inversion is enabled, the timer flip-flop is inverted at the same time.
Page 133 TMP92CH21 3.7.3 TMRA01 Run Register TA01RUN Bit symbol TA0RDE I2TA01 TA01PRUN TA1RUN TA0RUN (1100H) Read/Write Reset State Function Double IDLE2 TMRA01 UP counter UP counter (UC0) buffer 0: Stop prescaler (UC1) 0: Disable 1: Operate 0: Stop and clear 1: Enable 1: Run (Count up) TA0REG double buffer control Timer run/stop control...
Page 134 TMP92CH21 TMRA01 Mode Register TA01MOD Bit symbol TA01M1 TA01M0 PWM01 PWM00 TA1CLK1 TA1CLK0 TA0CLK1 TA0CLK0 (1104H) Read/Write Reset State Function Operation mode PWM cycle Source clock for TMRA1 Source clock for TMRA0 00: 8-bit timer mode 00: Reserved 00: TA0TRG 00: Reserved 01: φT1 01: φT1...
Page 135 TMP92CH21 TMRA23 Mode Register TA23MOD Bit symbol TA23M1 TA23M0 PWM21 PWM20 TA3CLK1 TA3CLK0 TA2CLK1 TA2CLK0 (110CH) Read/Write Reset State Function Operation mode PWM cycle Source clock for TMRA3 Source clock for TMRA2 00: 8-bit timer mode 00: Reserved 00: TA2TRG 00: Reserved 01: φT1 01: φT1...
Page 136 TMP92CH21 TMRA1 Flip-Flop Control Register TA1FFCR Bit symbol TA1FFC1 TA1FFC0 TA1FFIE TA1FFIS (1105H) Read/Write Reset State Read-modify- Function 00: Invert TA1FF TA1FF TA1FF write control for inversion 01: Set TA1FF instruction inversion select is prohibited. 10: Clear TA1FF 0: Disable 0: TMRA0 11: Don’t care 1: Enable...
Page 137 TMP92CH21 TMRA3 Flip-Flop Control Register TA3FFCR Bit symbol TA3FFC1 TA3FFC0 TA3FFIE TA3FFIS (110DH) Read/Write Reset State Read- Function 00: Invert TA3FF TA3FF TA3FF modify- control for inversion 01: Set TA3FF write inversion select instruction 10: Clear TA3FF 0: Disable 0: TMRA2 11: Don’t care prohibited.
Page 138 TMP92CH21 TMRA Register Symbol Address − TA0REG 1102H Undefined − TA1REG 1103H Undefined − TA2REG 110AH Undefined − TA3REG 110BH Undefined Note: Read-modify-write instruction is prohibited. Figure 3.7.9 8-Bit Timers Register 2009-06-19 92CH21-136...
Page 139 TMP92CH21 3.7.4 Operation in Each Mode (1) 8-bit timer mode Both TMRA0 and TMRA1 can be used independently as 8-bit interval timers. Generating interrupts at a fixed interval (using TMRA1) To generate interrupts at constant intervals using TMRA1 (INTTA1), first stop TMRA1 then set the operation mode, input clock and a cycle to TA01MOD and TA1REG register, respectively.
Page 140 TMP92CH21 Generating a 50 % duty ratio square wave pulse The state of the timer flip-flop (TA1FF1) is inverted at constant intervals and its status output via the timer output pin (TA1OUT). Example: To output a 2.4-μs square wave pulse from the TA1OUT pin at f = 40 MHz, use the following procedure to make the appropriate register settings.
Page 141 TMP92CH21 Making TMRA1 count up on the match signal from the TMRA0 comparator Select 8-bit timer mode and set the comparator output from TMRA0 to be the input clock to TMRA1. Comparator output (TMRA0 match) TMRA0 up counter (when TA0REG = 5) TMRA1 up counter (when TA1REG = 2) TMRA1 match output...
Page 142 TMP92CH21 The comparator match signal is output from TMRA0 each time the up counter UC0 matches TA0REG, though the up counter UC0 is not cleared. In the case of the TMRA1 comparator, the match detect signal is output on each comparator pulse on which the values in the up counter UC1 and TA1REG match.
Page 143 TMP92CH21 In this mode a programmable square wave is generated by inverting the timer output each time the 8-bit up counter (UC0) matches the value in one of the timer registers TA0REG or TA1REG. The value set in TA0REG must be smaller than the value set in TA1REG. Although the up counter for TMRA1 (UC1) is not used in this mode, TA01RUN<TA1RUN>...
Page 144 TMP92CH21 = 40 MHz) Example: To generate 1/4 duty 62.5 kHz pulses (at f 16 μs Calculate the value which should be set in the timer register. To obtain a frequency of 62.5 kHz, the pulse cycle t should be: t = 1/62.5 kHz = 16 μs φT1 (=(16/fc)s (at f = 40 MHz);...
Page 145 TMP92CH21 (4) 8-bit PWM output mode This mode is only valid for TMRA0. In this mode, a PWM pulse with the maximum resolution of 8 bits can be output. When TMRA0 is used the PWM pulse is output on the TA1OUT pin (which is also used as PC1).
Page 146 TMP92CH21 In this mode the value of the register buffer will be shifted into TA0REG if 2 overflow is detected when the TA0REG double buffer is enabled. Use of the double buffer facilitates the handling of low duty ratio waves. Match with TA0REG Up counter = Q Up counter = Q...
Page 147 TMP92CH21 Table 3.7.4 PWM Cycle PWM cycle TAxxMOD<PWMx1:0> System clock Clock gear − (x64) (x128) (x256) SYSCR0 SYSCR1 <SYSCK> <GEAR2:0> TAxxMOD<TAxCLK1:0> TAxxMOD<TAxCLK1:0> TAxxMOD<TAxCLK1:0> φT1(x2) φT4(x8) φT16(x32) φT1(x2) φT4(x8) φT16(x32) φT1(x2) φT4(x8) φT16(x32) − 1(fs) 1024/fs 4096/fs 16384/fs 2048/fs 8192/fs 32768/fs 4096/fs 16384/fs 65536/fs...
Page 148 TMP92CH21 External Memory Extension Function (MMU) By providing 3 local areas, the MMU function allows for the expansion of the program/data area up to 512 Mbytes. The recommended address memory map is shown in Figure 3.8.1 and Figure 3.8.2. However, when the memory used is less than 16 Mbytes, it is not necessary to set the MMU register.
Page 149 TMP92CH21 Memory controller setting pin (128 Mbytes) Address Memory Map pin (128 Mbytes) 000000H CS0 area Internal I/O, RAM 32 Kbytes 64 Mbytes(2 Mbytes × 32) COMMON-X (2 Mbytes) CS3 area 200000H 4 Mbytes LOCAL-X Bank 0 (2 Mbytes) 400000H LOCAL-Y Bank 0 (2 Mbytes)
Page 150 TMP92CH21 TMP92CH21 LOCAL-X LOCAL-Y LOCAL-Z , EA24, EA25 SDCS CSZA CSZF 64 Mbytes × 6 = 384 Mbytes 128 Mbytes 64 Mbytes CSZA CSZD 000000H BANK 0 BANK 0 BANK 0 BANK 48 Internal I/O and RAM CSZB CSZE BANK 16 BANK 64 CSZC CSZF...
Page 151 TMP92CH21 Memory controller setting pin (128 Mbytes) Address Memory Map pin (128 Mbytes) 000000H CS0 area Internal I/O, RAM 32 Kbytes COMMON-X (2 Mbytes) 200000H LOCAL-X (2 Mbytes) 3FE000H Internal boot ROM (8 Kbytes) 400000H LOCAL-Y (2 Mbytes) 600000H COMMON-Y (2 Mbytes) 800000H LOCAL-Z...
Page 152 TMP92CH21 3.8.2 Control Registers There are 12 MMU registers, covering 4 functions (program, data read, data write and LCDC display data), in each of 3 local areas (Local-X, Y and Z), providing easy data access. (Instructions for use) First, set the enable register and bank number for each LOCAL register. The relevant pin and memory settings should then be set to the ports and memory controller.
Page 153 TMP92CH21 (1) Program bank register The bank number used as program memory is set to these registers. It is not possible to change program bank number in the same local area. LOCAL-X Register for Program LOCALPX Bit symbol (01D0H) Read/Write Reset State Function Bank for...
Page 154 TMP92CH21 (2) LCD Display bank register The bank number used as LCD display memory is set to these registers. Since the bank registers for CPU and LCDC are prepared independently, the bank number for CPU (Program, Read data or Write data) can be changed during LCD display. LOCAL-X Register for LCDC Display Data LOCALLX Bit symbol...
Page 155 TMP92CH21 (3) Read data bank register The bank register number used as read data memory is set to these registers. The following is an example where the read data bank register of LOCAL-X is set to “1”. When “ld wa, (xix)” instruction is executed, the bank becomes effective only at the read cycle for xix address.
Page 156 TMP92CH21 (4) Write data bank register The bank number used as write data memory is set to these registers. The following is an example where the data bank register of LOCAL-X is set to “1”. When “ld (xix), wa” instruction is executed, the bank becomes effective only at the write cycle for xix address. (Example) xix, 200000h (localx), 81h...
Page 157 TMP92CH21 3.8.3 Setting Example Below is a setting example. Logical Physical Used as Memory Setting MMU Area Address Address Main COMMON-Z C00000H to FFFFFFH CSZA NOR flash routine 32 bits, (16 Mbytes, Character Bank 0 in 800000H to 000000H to 1 pcs) 1 wait LOCAL-Z...
Page 158 TMP92CH21 (b) Sub routine (Bank 0 in LOCAL-Y) Logical Physical Instruction Comment Address Address 400000H 400000H 000000H (localwy), 81H ; BANK 1 in LOCAL-Y is set as write data for LCD display RAM 4000xxH 0000xxH (locally), 81H ; BANK 1 in LOCAL-Y is set as LCD display data for LCD display RAM (localrz), 80H ;...
Page 159 TMP92CH21 Serial Channels The TMP92CH21 includes 2 serial I/O channels. For each channel, either UART mode (asynchronous transmission) or I/O interface mode (synchronous transmission) can be selected. I/O interface mode Mode 0: For transmitting and receiving I/O data using the synchronizing signal SCLK for extending I/O.
Page 160 TMP92CH21 • Mode 0 (I/O interface mode) Bit0 Transfer direction • Mode 1 (7-bit UART mode) No parity Start Bit0 Stop Parity Start Bit0 Parity Stop • Mode 2 (8-bit UART mode) No parity Start Bit0 Stop Parity Start Bit0 Parity Stop •...
Page 161 TMP92CH21 3.9.1 Block Diagrams Prescaler φT0 4 8 16 32 φT2 φT8 φT32 Serial clock generation circuit BR0CR<BR0CK1:0> TA0TRG (from TMRA0) BR0CR BR0ADD <BR0S3:0> <BR0K3:0> φT0 φT2 UART φT8 mode SIOCLK φT32 BR0CR <BR0ADDE> SC0MOD0 SC0MOD0 Baud rate generator <SC1:0> <SM1:0>...
Page 162 TMP92CH21 Prescaler φT0 4 8 16 32 φT2 φT8 φT32 Serial clock generation circuit BR1CR<BR1CK1:0> BR1CR BR1ADD TA0TRG <BR1S3:0> <BR1K3:0> (from TMRA0) φT0 φT2 UART φT8 mode SIOCLK φT32 BR1CR <BR1ADDE> SC1MOD0 SC1MOD0 Baud rate generator <SC1:0> <SM1:0> ÷2 SCLK1 I/O interface mode SC1CR <IOC>...
Page 163 TMP92CH21 3.9.2 Operation for Each Circuit (1) SIO Prescaler and prescaler clock select There is a 6-bit prescaler for waking serial clock. The prescaler can be run by selecting the baud rate generator as the waking serial clock. Table 3.9.2 shows prescaler clock resolution into the baud rate generator. Table 3.9.2 Prescaler Clock Resolution to Baud Rate Generator Baud rate generator input clock System clock...
Page 164 TMP92CH21 (2) Baud rate generator The baud rate generator is a circuit which generates transmission and receiving clocks that determine the transfer rate of the serial channels. The input clock to the baud rate generator, φT0, φT2, φT8 or φT32, is generated by the 6-bit SIO prescaler, which is shared by the timers.
Page 165 TMP92CH21 • Integer divider (N divider) For example, when the source clock frequency (f ) is 39.3216 MHz, the input clock is φT2 (f /32), the frequency divider N (BR0CR<BR0S3:0>) = 8, and BR0CR<BR0ADDE> = 0, the baud rate in UART mode is as follows: * Clock condition Clock gear : 1/1 Input clock of baud rate generator...
Page 166 TMP92CH21 Table 3.9.3 Selection of Transfer Rate (1) (when baud rate generator is used and BR0CR<BR0ADDE> = 0) Unit (Kbps) Input Clock φT0 φT2 φT8 φT32 [MHz] /16) /64) /256) Frequency Divider 9.8304 76.800 19.200 4.800 1.200 ↑ 38.400 9.600 2.400 0.600 ↑...
Page 167 TMP92CH21 (3) Serial clock generation circuit This circuit generates the basic clock for transmitting and receiving data. • In I/O interface mode In SCLK output mode with the setting SC0CR<IOC> = 0, the basic clock is generated by dividing the output of the baud rate generator by 2, as described previously.
Page 168 TMP92CH21 (6) The receiving buffers To prevent overrun errors, the receiving buffers are arranged in a double buffer structure. Received data is stored one bit at a time in receiving buffer 1 (which is a shift register). When 7 or 8 bits of data have been stored in receiving buffer 1, the stored data is transferred to receiving buffer 2 (SC0BUF);...
Page 169 TMP92CH21 Handshake function Use of pin allows data to be sent in units of one frame; thus, overrun CTS0 errors can be avoided. The handshake function is enabled or disabled by the SC0MOD<CTSE> setting. When the pin goes high on completion of the current data send, data CTS0 transmission is halted until the pin goes low again.
Page 170 TMP92CH21 (9) Transmission buffer The transmission buffer (SC0BUF) shifts out and sends the transmission data written from the CPU in order from the least significant bit (LSB). When all the bits are shifted out, the transmission buffer becomes empty and generates an INTTX0 interrupt.
Page 171 TMP92CH21 Parity error <PERR> The parity generated for the data shifted into receiving buffer 2 (SC0BUF) is compared with the parity bit received via the RXD pin. If they are not equal, a parity error is generated. Framing error <FERR> The stop bit for the received data is sampled three times around the center.
Page 172 TMP92CH21 (12) Timing generation In UART mode Receiving 8 Bits, 7 Bits + Parity, Mode 9 Bits 8 Bits + Parity (Note) (Note) 7 Bits Center of last bit Center of last bit Interrupt Timing Center of stop bit (bit8) (parity bit) Framing Error Timing Center of stop bit...
Page 173 TMP92CH21 3.9.3 SC0MOD0 Bit symbol CTSE (1202H) Read/Write Reset State Function Transfer Hand Receive Wakeup Serial transmission mode Serial transmission clock data bit8 shake function function (UART) 00: I/O interface mode 0: CTS 0: Receive 0: Disable 00: TMRA0 trigger 01: 7-bit UART mode disable disable...
Page 174 TMP92CH21 SC1MOD0 Bit symbol CTSE (120AH) Read/Write Reset State Function Transfer Hand Receive Wakeup Serial transmission mode Serial transmission clock data bit8 shake function function (UART) 00: I/O interface mode 0: CTS 0: Receive 0: Disable 00: TMRA0 trigger 01: 7-bit UART mode disable disable 1: Enable...
Page 175 TMP92CH21 SC0CR Bit symbol EVEN OERR PERR FERR SCLKS (1201H) Read/Write R (Cleared to 0 when read) Reset State Undefined Function Received Parity Parity 0: SCLK0 0: Baud rate 1: Error data bit8 0: Odd addition generator 1: Even 0: Disable 1: SCLK0 Overrun Parity...
Page 176 TMP92CH21 SC1CR Bit symbol EVEN OERR PERR FERR SCLKS (1209H) Read/Write R (cleared to 0 when read) Reset State Undefined Function Received Parity Parity 0: SCLK1 0: Baud rate 1: Error data bit8 addition generator 0: Odd 0: Disable 1: SCLK1 1: Even Overrun Parity...
Page 177 TMP92CH21 − BR0CR Bit symbol BR0ADDE BR0CK1 BR0CK0 BR0S3 BR0S2 BR0S1 BR0S0 (1203H) Read/Write Reset State +(16 − K)/16 00: φT0 Function Always write “0”. division 01: φT2 Divided frequency setting 0: Disable 10: φT8 1: Enable 11: φT32 +(16 − K)/16 division enable Setting the input clock of baud rate generator Internal clock φT0 Disable...
Page 178 TMP92CH21 − BR1CR Bit symbol BR1ADDE BR1CK1 BR1CK0 BR1S3 BR1S2 BR1S1 BR1S0 (120BH) Read/Write Reset State + (16 − K)/16 00: φT0 Function Always write “0”. division 01: φT2 Divided frequency setting 10: φT8 0: Disable 11: φT32 1: Enable + (16 −...
Page 179 TMP92CH21 (Transmission) SC0BUF (1200H) (Receiving) Note: Prohibit read-modify-write for SC0BUF. Figure 3.9.13 Serial Transmission/Receiving Buffer Registers (Channel 0, SC0BUF) Bit symbol I2S0 FDPX0 SC0MOD1 Read/Write (1205H) Reset State Function IDLE2 Duplex 0: Stop 0: Half 1: Run 1: Full Figure 3.9.14 Serial Mode Control Register 1 (Channel 0, SC0MOD1) (Transmission) SC1BUF (1208H)
Page 180 TMP92CH21 3.9.4 Operation in Each Mode (1) Mode 0 (I/O interface mode) This mode allows an increase in the number of I/O pins available for transmitting data to or receiving data from an external shift register. This mode includes the SCLK output mode to output synchronous clock SCLK, and SCLK input mode to input external synchronous clock SCLK.
Page 181 TMP92CH21 Transmission In SCLK output mode 8-bit data and a synchronous clock are output on the TXD0 and SCLK0 pins respectively each time the CPU writes data to the transmission buffer. When all data is output, INTES0<ITX0C> will be set to generate the INTTX0 interrupt.
Page 182 TMP92CH21 Receiving In SCLK output mode the synchronous clock is output on the SCLK0 pin and the data is shifted to receiving buffer 1. This is initiated when the receive interrupt flag INTES0<IRX0C> is cleared as the received data is read. When 8-bit data is received, the data is transferred to receiving buffer 2 (SC0BUF) following the timing shown below and INTES0<IRX0C>...
Page 183 TMP92CH21 Transmission and receiving (Full duplex mode) When full duplex mode is used, set the receive interrupt level to 0, and only set the interrupt level (from 1 to 6) of the transmit interrupt. Ensure that the program which transmits the interrupt reads the receiving buffer before setting the next transmit data.
Page 184 TMP92CH21 (2) Mode 1 (7-bit UART mode) 7-bit UART mode is selected by setting the serial channel mode register SC0MOD0<SM1:0> field to 01. In this mode a parity bit can be added. Use of a parity bit is enabled or disabled by the setting of the serial channel control register SC0CR<PE>...
Page 185 TMP92CH21 Main settings ← X − − PFCR Set PF1 to function as the RXD0 pin. ← − − − PFFC ← − − SC0MOD0 Enable receiving in 8-bit UART mode. ← − − − − SC0CR Add odd parity. ←...
Page 186 TMP92CH21 Protocol Select 9-bit UART mode on the master and slave controllers. Set the SC0MOD0<WU> bit on each slave controller to 1 to enable data receiving. 3. The master controller transmits data one frame at a time. Each frame includes an 8-bit select code which identifies a slave controller.
Page 187 TMP92CH21 Setting example: To link two slave controllers serially with the master controller using the internal clock f as the transfer clock. Master Slave1 Slave 2 Select code Select code 00001010 00000001 • Setting the master controller Main ← X X X X X −...
Page 188 TMP92CH21 3.9.5 Support for IrDA SIO0 includes support for the IrDA 1.0 infrared data communication specification. Figure 3.9.24 shows the block diagram. TXD0 Transmission data IR modulator IR transmitter & LED IR output SIO0 Modem RXD0 Receive IR receiver IR demodulator data IR input TMP92CH21...
Page 189 TMP92CH21 (3) Data format The data format is fixed as follows: • Data length: 8 bits • Parity bits: none • Stop bits: 1 bit (4) SFR Figure 3.9.27 shows the control register SIRCR. Set SIRCR data while SIO0 is stopped.
Page 190 TMP92CH21 (5) Notes Baud rate for IrDA When IrDA is operated, set 01 to SC0MOD0<SC1:0> to generate baud rate. Settings other than the above (TA0TRG, f and SCLK0 input) cannot be used. The pulse width for transmission The IrDA 1.0 specification is defined in Table 3.9.4. Table 3.9.4 Baud Rate and Pulse Width Specifications Rate Tolerance Pulse Width...
Page 191 TMP92CH21 (6) Using IrDA 115.2 Kbps with USB When the system uses USB , set f to 9.0 MHz. In this case, the IrDA cannot be OSCH 115.2 Kbps without using the (16 − K)/16 division function. Therefore, only in this case, the following conditions can be used. (Setting condition) •...
Page 192 TMP92CH21 SIRCR Bit symbol PLSEL RXSEL TXEN RXEN SIRWD3 SIRWD2 SIRWD1 SIRWD0 (1207H) Read/Write Reset State Function Select Receive Transmit Receive Select receive pulse width transmit data Set effective pulse width to equal to or more than 2x × 0: Disable 0: Disable pulse width (value + 1) + 100 ns...
Page 193 TMP92CH21 3.10 USB Controller 3.10.1 Outline This USB controller (UDC) is designed to support a variety of serial links in the construction of a USB system. The outline is as follows: (1) Compliant with USB rev1.1 (2) Full-speed: 12 Mbps (low-speed (1.5 Mbps) not supported) (3) Auto bus enumeration with 384-byte descriptor RAM (4) Supports 3 kinds of transfer type: Control, interrupt and bulk Endpoint 0:...
Page 194 TMP92CH21 3.10.1.1 System Configuration The USB controller (UDC) consists of the following 3 blocks. 900/H1 CPU I/F (details given in Section 3.10.2, below). UDC core block (DPLL, SIE, IFM and PWM), request controller, descriptor RAM and 4 endpoint FIFO (details given in Section 3.10.3, below). USB transceiver Descriptor RAM 384 bytes...
Page 195 TMP92CH21 3.10.1.2 Example USB host USB device USB host TMP92CH21 Connector Connector VBUS INTx (detect rising) 9MHz PorTXX cable D− OFF at OFF at “H” "H" The above setting is required when using the TMP92CH21’s USB controller. 1) Pull-up of D ・...
Page 196 TMP92CH21 3.10.2 900/H1 CPU I/F The 900/H1 CPU I/F is a bridge between the 900/H1 CPU and the UDC. Its main functions are as follows:. • INTUSB (interrupt from UDC) generation • A bridge for SFR • USB clock control (48 MHz) 3.10.2.1 SFRs The 900/H1 CPU I/F incorporates the following SFRs to control the UDC and USB transceiver.
Page 197 TMP92CH21 3.10.2.2 USBCR1 Register This register is used to set USB clock enables, transceiver enable etc. − bit Symbol TRNS_USE WAKEUP SPEED USBCLKE USBCR1 (07F8H) Read/Write Reset State Function Always write “0” • TRNS_USE (Bit7) 0: Disable USB transceiver 1: Enable USB transceiver Always set to “1”...
Page 198 TMP92CH21 3.10.2.3 USBINTFRn, MRn Register These SFRs control the INTUSB (only one interrupt to CPU) using the 23 interrupt sources output by the UDC. The USBINTMRn are mask registers and the USBINTFRn are flag registers. In the INTUSB routine, execute operations according to generated interrupt source after checking USBINTFRn.
Page 199 TMP92CH21 bit Symbol INT_URST_STR USBINTFR1 INT_URST_END INT_SUS INT_RESUME INT_CLKSTOP INT_CLKON (07F0H) Read/Write Reset State Function When read 0: Not generate interrupt When write 0: Clear flag 1: − 1: Generate interrupt Note: The above interrupts can release Halt state from IDLE2 and IDLE1 mode. (STOP mode cannot be released) *Those 6 interrupts of all 24 INTUSB sources can release Halt state from IDLE1 mode.
Page 200 TMP92CH21 bit Symbol EP1_FULL_A EP1_Empty_A EP1_FULL_B EP1_Empty_B EP2_FULL_A EP2_Empty_A EP2_FULL_B EP2_Empty_B USBINTFR2 (07F1H) Read/Write Reset State Function When read 0: Not generate interrupt When write 0: Clear flag 1: − 1: Generate interrupt Note: The above interrupt can release Halt state from IDLE2 mode. (IDLE1 and STOP mode cannot be released.) bit Symbol USBINTFR3 EP3_FULL_A...
Page 201 TMP92CH21 bit Symbol INT_SETUP INT_EP0 INT_STAS INT_STASN INT_EP1N INT_EP2N INT_EP3N EP2_Empty_B USBINTFR4 (07F3H) Read/Write Reset State Function When read 0: Not generate interrupt When write 0: Clear flag 1: − 1: Generate interrupt Note: The above interrupt can release Halt state from IDLE2 mode. (IDLE1 and STOP mode cannot be released.) •...
Page 202 TMP92CH21 • INT_STASN (Bit4) This is the flag register for INT_STASN (change host status stage - interrupt). This is set to “1” when the USB host changes to status stage at the Control read transfer. This interrupt is needed if data length is less than wLength (specified by the host).
Page 203 TMP92CH21 bit Symbol USBINTMR1 MSK_URST_STR MSK_URST_END MSK_SUS MSK_RESUME MSK_CLKSTOP MSK_CLKON (07F4H) Read/Write Reset State Function When read 0: not masked When write 0: Clear flag 1: − 1: masked • MSK_URST_STR (Bit7) This is the mask register for USBINTFR1<INT_URST_STR>. • MSK_URST_END (Bit6) This is the mask register for USBINTFR1<INT_URST_END>.
Page 204 TMP92CH21 bit Symbol EP1_MSK_FA EP1_MSK_EA EP1_MSK_FB EP1_MSK_EB EP2_MSK_FA EP2_MSK_EA EP2_MSK_FB EP2_MSK_EB USBINTMR2 (07F5H) Read/Write Reset State Function When read 0: not masked When write 0: Clear flag 1: − 1: masked • EP1/2_MSK_FA/FB/EA/EB This is the mask register for USBINTFR2<EPx_FULL_A/B> or <EPx_Empty_A/B>.
Page 205 TMP92CH21 bit Symbol USBINTMR4 MSK_SETUP MSK_EP0 MSK_STAS MSK_STASN MSK_EP1N MSK_EP2N MSK_EP3N (07F7H) Read/Write Reset State Function When read 0: not masked When write 0: Clear flag 1: − 1: masked • MSK_SETUP (Bit7) This is the mask register for USBINTFR4<INT_SETUP>. •...
Page 206 TMP92CH21 3.10.3 UDC CORE 3.10.3.1 SFRs The UDC CORE has the following SFRs to control the UDC and USB transceiver. FIFO Endpoint 0 to 3 FIFO register Device request bmRequestType register bRequest register wValue_L register wValue_H register wIndex_L register wIndex_H register wLength_L register...
Page 207 TMP92CH21 Table 3.10.2 UDC CORE SFRs (1/2) Address Read/Write SFR Symbol 0500H Descriptor RAM0 0501H Descriptor RAM1 0502H Descriptor RAM2 0503H Descriptor RAM3 067DH Descriptor RAM381 067EH Descriptor RAM382 067FH Descriptor RAM383 0780H ENDPOINT0 0781H ENDPOINT1 0782H ENDPOINT2 0783H ENDPOINT3 0789H EP1_MODE 078AH...
Page 208 TMP92CH21 Table 3.10.3 UDC CORE SFRs (2/2) Address Read/Write SFR Symbol 07C0H bmRequestType 07C1H bRequest 07C2H wValue_L 07C3H wValue_H 07C4H wIndex_L 07C5H wIndex_H 07C6H wLength_L 07C7H wLength_H 07C8H Setup Received 07C9H Current_Config 07CAH Standard Request 07CBH Request 07CCH DATASET1 07CDH DATASET2 07CEH USB_STATE...
Page 209 TMP92CH21 3.10.3.2 EPx_FIFO Register (x: 0 to 3) This register is prepared for each endpoint independently. This is the window register from or to FIFO RAM. In the auto bus enumeration, the request controller in UDC sets the mode, which is defined by the endpoint descriptor, for each endpoint automatically.
Page 210 TMP92CH21 3.10.3.3 bmRequestType Register This register shows the bmRequestType field of the device request. bmRequestType bit Symbol DIRECTION REQ_TYPE1 REQ_TYPE0 RECIPIENT4 RECIPIENT3 RECIPIENT2 RECIPIENT1 RECIPIENT0 (07C0H) Read/Write Reset State DIRECTION (Bit7) 0: from host to device 1: from device to host REQ_TYPE [1:0] (Bit6 to bit5) 00: Standard 01: Class...
Page 211 TMP92CH21 3.10.3.5 wValue Register There are 2 registers; the wValue_L register and wValue_H register. wValue_L shows the lower-byte of the wValue field of the device request, and wValue_H register shows the upper byte. wValue_L bit Symbol VALUE_L7 VALUE_L6 VALUE_L5 VALUE_L4 VALUE_L3 VALUE_L2 VALUE_L1...
Page 212 TMP92CH21 3.10.3.8 Setup Received Register This register informs the UDC that an application program has recognized the INT_SETUP interrupt. SetupReceived bit Symbol (07C8H) Read/Write Reset State If this register is accessed by an application program, the UDC disables access to the EP0’s FIFO RAM, because the UDC recognizes the device request has been received.
Page 213 TMP92CH21 3.10.3.10 Standard Request Register This register shows the standard request currently being executed. Any bit which is set to “1” shows a request currently being executed. Standard Request bit Symbol S_INTERFACE G_INTERFACE S_CONFIG G_CONFIG G_DESCRIPT S_FEATURE C_FEATURE G_STATUS (07CAH) Read/Write Reset State S_INTERFACE...
Page 214 TMP92CH21 3.10.3.12 DATASET Register This register shows whether FIFO contains data or not. The application program can access this register to check whether FIFO contains data or not. In receive status, when a valid data transfer from the USB host has finished, the bit which corresponds to the applicable endpoint is set to “1”...
Page 215 TMP92CH21 Note1: In receive mode, if the endpoint bits corresponding to packet-A or packet-Bare “1”, read the required packet-number data after checking EPx_SIZE<PKT_ACTIVE>. Note2: In transmit mode, if both A and B bits are not “1”, this means there is space in FIFO. So, write data of payload or less to FIFO.
Page 216 TMP92CH21 3.10.3.13 EPx_STATUS Register (x: 0 to 7) These registers are status registers for each endpoint. The <SUSPEND> is common to all endpoints. TOGGLE SUSPEND STATUS[2] STATUS[1] STATUS[0] FIFO_DISABLE STAGE_ERR EP0_STATUS bit Symbol (0790H) Read/Write Reset State EP1_STATUS TOGGLE SUSPEND STATUS[2] STATUS[1] STATUS[0]...
Page 217 TMP92CH21 STATUS [2:0] These bits show status of UDC endpoint. (Bit4 to bit2) The status shows whether transfer is possible or not, and the results of the transfer. . These depend on transfer type. (For the Isochronous transfer type, refer to 3.10.6.) 000: READY Receiving: Device can be received.
Page 218 TMP92CH21 FIFO_DISABLE (Bit1) This bit symbol shows FIFO status, except for EP0. If the FIFO is set to disabled, the UDC transmits NAK 0: FIFO enabled 1: FIFO disabled handshake for all transfers. Disabled or enabled status is set by the COMMAND register.
Page 219 TMP92CH21 3.10.3.14 EPx_SIZE Register (x: 0 to 7) These registers have the following functions. In receive mode, showing the 1-packet data number which was received correctly. b) In transmit mode, showing payload size. Showing length value when short packet is transferred. It is not necessary to read this register when it is transmitting.
Page 220 TMP92CH21 DATASIZE9 DATASIZE8 DATASIZE7 bit Symbol EP1_SIZE_L_B Read/Write (07A1H) Reset State DATASIZE9 DATASIZE8 DATASIZE7 bit Symbol EP2_SIZE_L_B (07A2H) Read/Write Reset State EP3_SIZE_L_B DATASIZE9 DATASIZE8 DATASIZE7 bit Symbol (07A3H) Read/Write Reset State EP4_SIZE_L_B DATASIZE9 DATASIZE8 DATASIZE7 bit Symbol (07A4H) Read/Write Reset State EP5_SIZE_L_B DATASIZE9 DATASIZE8...
Page 221 TMP92CH21 EP1_SIZE_H_A DATASIZE9 DATASIZE8 DATASIZE7 bit Symbol (07A9H) Read/Write Reset State EP2_SIZE_H_A DATASIZE9 DATASIZE8 DATASIZE7 bit Symbol (07AAH) Read/Write Reset State EP3_SIZE_H_A DATASIZE9 DATASIZE8 DATASIZE7 bit Symbol (07ABH) Read/Write Reset State EP4_SIZE_H_A DATASIZE9 DATASIZE8 DATASIZE7 bit Symbol (07ACH) Read/Write Reset State EP5_SIZE_H_A DATASIZE9 DATASIZE8...
Page 222 TMP92CH21 DATASIZE9 DATASIZE8 DATASIZE7 EP1_SIZE_H_B bit Symbol (07B1H) Read/Write Reset State EP2_SIZE_H_B DATASIZE9 DATASIZE8 DATASIZE7 bit Symbol (07B2H) Read/Write Reset State EP3_SIZE_H_B DATASIZE9 DATASIZE8 DATASIZE7 bit Symbol (07B3H) Read/Write Reset State EP4_SIZE_H_B DATASIZE9 DATASIZE8 DATASIZE7 bit Symbol (07B4H) Read/Write Reset State EP5_SIZE_H_B DATASIZE9 DATASIZE8...
Page 223 TMP92CH21 3.10.3.15 FRAME Register This register shows the frame number which is issued with SOF token from the host and is used for Isochronous transfer type. Each HIGH and LOW register shows upper and lower bits. − FRAME_L bit Symbol T[6] T[5] T[4]...
Page 224 TMP92CH21 3.10.3.17 EOP Register This register is used when a control transfer type dataphase terminates or when a short packet is transmitting bulk-IN or interrupt-IN. EP7_EOPB EP6_EOPB EP5_EOPB EP4_EOPB EP3_EOPB EP2_EOPB EP1_EOPB EP0_EOPB bit Symbol (07CFH) Read/Write Reset State Note1: EOP<EP7_EOPB, EP6_EOPB, EP5_EOPB, EP4_EOPB> registers are not used in the TMP92CH21. Note2: When writing to this register, a recovery time of 5clocks at 12MHz is needed.
Page 225 TMP92CH21 3.10.3.18 Port Status Register This register is used when a printer class request is received. In the case of a GET_PORT_STATUS request, the UDC operates automatically using this data. Port Status bit Symbol Reserved7 Reserved6 PaperError Select NotError Reserved2 Reserved1 Reserved0 (07E0H)
Page 226 TMP92CH21 3.10.3.20 Request Mode Register This register sets the answer for Class Request either automatically in hardware or by control through software. Each bit represents a kind of request. When relevant bit in this register is set to “0”, the answer is executed automatically by hardware.
Page 227 TMP92CH21 3.10.3.21 COMMAND Register This register sets COMMAND at each endpoint. This register can be set to select endpoint in bit6 to bit4 and kind of COMMAND in bit3 to bit0. COMMAND for endpoint that is supported is ignored. COMMAND bit Symbol EP[2] EP[1]...
Page 228 TMP92CH21 1000: FIFO_ENABLE This COMMAND sets FIFO of corresponding endpoint to enable (EP1 to EP3). If FIFO is set to disable by FIFO_DISABLE COMMAND, this command is used for release of disable condition. If set while receiving packet, this becomes valid from next token.
Page 229 TMP92CH21 3.10.3.22 INT_Control Register INT_STATUS_NAK interrupt is disabled and enabled by the value that is written to this register. This is initialized to disable by external reset. When setup packet is received, it becomes disabled. INT_Control Status_nak bit Symbol (07D6H) Read/Write Reset State In control read transfer, if the host terminates a dataphase with small data length...
Page 230 TMP92CH21 3.10.3.24 EPx_MODE Register (x: 1 to 3) This register sets transfer mode of endpoint (EP1 to EP3). If SET_CONFIG and SET_INTERFACE processing is set to software control, this control must use appointed config or interface. Access this register to set mode. Payload[2] Payload[1] Payload[0]...
Page 231 TMP92CH21 3.10.3.25 EPx_SINGLE Register This register sets mode of FIFO in each endpoint (SINGLE/DUAL). EPx_SINGLE1 EP3_SELECT EP2_SELECT EP1_SELECT EP3_SINGLE EP2_SINGLE EP1_SINGLE bit Symbol (07D1H) Read/Write Reset State Note: Endpoint 3 supports only SINGLE mode in the TMP92CH21. Bit number 0: No use 1: EP1_SINGLE 2: EP2_SINGLE 3: EP3_SINGLE...
Page 232 TMP92CH21 3.10.3.27 USBREADY Register This register informs finishing writing data to descriptor RAM on UDC. After assigned data to descriptor RAM, write “0” to bit0. USBREADY USBREADY bit Symbol (07E6H) Read/Write Reset State USBREADY (Bit0) 0: Writing to descriptor RAM has finished. 1: Writing to descriptor RAM is enabled.
Page 233 TMP92CH21 3.10.3.28 Set Descriptor STALL Register This register sets whether returns STALL automatically in data stage or status stage for Set Descriptor Request. Set Descriptor STALL S_D_STALL bit Symbol (07E8H) Read/Write Reset State Bit0: S_D_STALL 0: Software control (Default) 1: Automatically STALL 3.10.3.29 Descriptor RAM This register is used for store descriptor to RAM.
Page 234 TMP92CH21 3.10.4 Descriptor RAM This area stores the descriptor that is defined in USB. Device, Config, Interface, Endpoint and String descriptor must set to RAM using the following format. Device descriptor 18 bytes Config 1 descriptor (Interfaces, endpoints) 255 bytes or less Config 2 descriptor (Interfaces, ENDPOINT) 255 bytes or less...
Page 235 USB Spec 1.00 503H bcdUSB (H) IFC’s specify own 504H bDeviceClass 505H bDeviceSubClass 506H bDeviceProtocol 507H bMaxPacketSize0 508H bVendor (L) Toshiba 509H bVendor (H) 50AH IdProduct (L) 50BH IdProduct (H) 50CH bcdDevice (L) Release 1.00 50DH bcdDevice (H) 50EH bManufacture...
Page 236 TMP92CH21 Address Data Description Description Interface0 Descriptor AlternateSetting1 52BH bLength 52CH bDescriptorType Interface Descriptor 52DH bInterfaceNumber 52EH bAlternateSetting AlternateSetting1 52FH bNumEndpoints 530H bInterfaceClass 531H bInterfaceSubClass 532H bInterfaceProtocol 533H iInterface Endoint1 Descriptor 534H bLength 535H bDescriptorType Endpoint Descriptor 536H bEndpointAddress 537H bmAttributes BULK 538H...
Page 237 565H bDescriptorType String Descriptor 566H bString Language ID 0x0409 567H bString String Descriptor1 568H bLength 569H bDescriptorType String Descriptor 56AH bString (Toshiba) 56BH bString 56CH bString 56DH bString 56EH bString 56FH bStrIng 570H bString 571H bString 572H bString 573H...
Page 238 TMP92CH21 3.10.5 Device Request 3.10.5.1 Standard request UDC support automatically answers in standard request. 1) GET_STATUS Request This request automatically returns to status that is determined by receive side. bmRequestType bRequest wValue wIndex wLength Data 10000000B GET_STATUS Device, interface or endpoint status 10000001B Interface...
Page 239 TMP92CH21 (2) CLEAR_FEATURE request This request clears or disables the relevant function. bmRequestType bRequest wValue wIndex wLength Data 00000000B CLEAR_ Feature None FEATURE selector Interface 00000001B endpoint 00000010B • Reception side device Feature selector: 1 Present remote wakeup setting is disabled. Feature selector: except 1 STALL state •...
Page 240 TMP92CH21 (4) SET_ADDRESS request This request sets the device address. Answer subsequent requests using this device address. Answer requests using the current device address until the status stage of this request is terminated normally. bmRequestType bRequest wValue wIndex wLength Data 00000000B SET_ADDRESS Device Address...
Page 241 TMP92CH21 (6) SET_DESCRIPTOR request This request sets or enables the relevant function. bmRequestType bRequest wValue wIndex wLength Data 00000000B SET_ Descriptor type Descriptor Descriptor Descriptor length Descriptor index Language ID Automatic answer of this request is not supported. According to INT_SETUP interrupt, if the request received was identified as a SET_DESCRIPTOR request, take back data after confirming EP0_DSET_A bit of DATASET register is “1”.
Page 242 TMP92CH21 (9) GET_INTERFACE request This request returns AlternateSetting value that is set by specified interface. bmRequestType bRequest wValue wIndex wLength Data 10000001B GET_ Interface Alternate INTERFACE setting If there is no specified interface, it enters STALL state. Note: If the descriptor is configured no endpoint in interface, use the software answer since automatic answer of GET_INTERFACE request by hardware is not supported.
Page 243 TMP92CH21 3.10.5.2 Printer Class Request UDC does not support “Automatic answer” of printer class request. Processing of Class requests is the same as for vendor requests when answering INT_SETUP interrupts. (1) GET_PORT_STATUS request This request transmits Port Status to host. bmRequestType bRequest wValue...
Page 244 TMP92CH21 (3) Vendor request (Class request) UDC does not support “Automatic answer” of Vendor requests. According to INT_SETUP interrupt, access the register in which the device request is stored, and identify the request. If this request is a Vendor request, control the UDC externally, and process the Vendor request.
Page 245 TMP92CH21 (b) Control write/request There is no dataphase bmRequestType bRequest wValue wIndex wLength Data 010000xxB Vendor specific Vendor specific Vendor specific None When INT_SETUP is received, identify contents of request bmRequestType, bRequest, wValue, wIndex, wLength registers,and process each request. According to application, access Setup_Received register after request has been identified.
Page 246 TMP92CH21 Below is control flow in UDC as seen from application. Start up Setting each EP mode in Set_Config (Interface) IDLE Standard request Printerclass request Enumeration Identify request RD Access to SetupReceived register Control RD transfer Control WR transfer Get_Vendor_Request Set_Vendor_Request process process...
Page 247 TMP92CH21 3.10.6 Transfer mode and Protocol Transaction The UDC performs the following automatically in hardware; • Receive packet • Determine address endpoint transfer mode • Error process • Confirm toggle bit CRC of data receiving packet • Generate toggle bit CRC of data transmitting packet, etc •...
Page 248 TMP92CH21 (2) Transfer mode UDC supports FULL speed transfer mode. • FULL speed device Control transfer type Interrupt transfer type Bulk transfer type Isochronous transfer type The following is an explanation of UDC operation in each transfer mode. The explanation is of data flow up until FIFO. (a) Bulk transfer type Bulk transfer type warrants transferring no error between host and function by using detect error and retry.
Page 249 TMP92CH21 (a-1) Transmission bulk mode Below is the transaction format for bulk transfer during transmitting. • Token: IN • Data: DATA0/DATA1, NAK, STALL • Handshake: ACK Control flow Below is the control-flow when the UDC receives an IN token. The token packet is received and the address endpoint number error is confirmed, and it checks whether the relevant endpoint transfer mode corresponds with the IN token.
Page 250 TMP92CH21 IDLE Receive IN token Error ConfirmToken packet • PID • Address • Endpoint • Transfer mode • Error Invalid Confirm Handshake answer Stall • Confirm STATUS register (Status) • Confirm DATASET register FIFO empty More than MAX Generate DATA PID Transmit NAK Transmit STALL payload...
Page 251 TMP92CH21 (a-2) Receiving bulk mode Below is the transaction format for receiving bulk transfer type. • Token: OUT • Data: DATA0/DATA1 • Handshake: ACK, NAK, STALL Control flow Below is the control-flow when the UDC receives an IN token. The token packet is received and the address endpoint number error is confirmed, and it checks whether the relevant endpoint transfer mode corresponds with the OUT token.
Page 252 TMP92CH21 IDLE Receive OUT token Confirm Token packet • PID • Address • Endpoint • Transfer mode • Error Invalid Confirm Status Stall • Confirm STATUS register (status) • Confirm FIFO’s condition FIFO FULL Error transaction • Set STATUS at RX_ERR •...
Page 253 TMP92CH21 (b) Interrupt transfer type Interrupt transfer type uses the same transaction format as transmission bulk transfer. For transmission using toggle bit, hardware setting and answer in the UDC are the same as for transmission bulk transfer. Interrupt transfer can be transferred without using toggle bit.
Page 254 TMP92CH21 (c) Control transfer type Control transfer type is configured in the three stages below. • Setup stage • Data stage • Status stage Data stage is sometimes skipped. Each stage is configured in one or several transactions. The UDC executes each transaction while managing three stages in hardware.
Page 255 TMP92CH21 Data packet is received. Device request of 8 bytes from SIE in UDC is transferred to the request register below. • bmRequestType register • bmRequest register • wValue register • wIndex register • wLength register After last data is transferred, counted CRC is compared with transferred CRC.
Page 256 TMP92CH21 IDLE Receive SETUP token Error Confirm Token packet • PID • Address • Endpoint • Transfer mode • Error Invalid Error transaction • Set STATUS to RX_ERR • Put back FIFO address point Confirm Status • Confirmation STATUS register (Status) Except DATA0 PID Confirm DATA PID •...
Page 257 TMP92CH21 (c-2) Data stage Data stage is configured by one or several transactions based on toggle sequence. The transaction is the same as for format transmission or receiving bulk transaction except for the following differences: • Toggle bit starts from “1” by SETUP stage. •...
Page 258 TMP92CH21 If ACK handshake from host is received, • Set STATU to READY. • Assert INT_STATUS interrupt. It finishes normally by the above transaction. If a time out occurs without receiving ACK from host, • Set STATUS register to TX_ERR and state returns to IDLE, and wait for restring status stage.
Page 259 TMP92CH21 (c-4) Stage management The UDC manages each stage of control transfer by hardware. Each stage is changed by receiving token from USB host, or CPU accesses register. Each stage in control transfer type has to process combination software. UDC detects the following contents from 8-byte data in SETUP stage. The stage is managed by determining control transfer type.
Page 260 TMP92CH21 Stage change condition of control read transfer type Receive SETUP token from host • Start setup stage in UDC. • Receive data in request normally and judge. And assert INT_SETUP interrupt externally. • Change data stage in the UDC. Receive IN token from host •...
Page 261 TMP92CH21 Stage change condition of control writes transfer type Receive SETUP token from host. • Start setup stage in the UDC. • Receive data in request normally and judge. And assert INT_SETUP interrupt externally. • Change data stage in the UDC. Receive OUT token from host.
Page 262 TMP92CH21 Stage change condition of control write (no data stage) transfer type Receive SETUP token from host • Start setup stage in UDC. • Receive data in request normally and judge. And assert INT_SETUP interrupt externally. • Change data stage in the UDC. Receive IN token from host •...
Page 263 TMP92CH21 (d) Isochronous transfer type Isochronous transfer type is guaranteed transfer by data number that is limited to each frame. However, this transfer does not retry when an error occurs. Therefore, Isochronous transfer type transfer only 2 phases (token, data) and it does not use handshake phase.
Page 264 TMP92CH21 Below is transaction when SOF token is received from host. • Change the packet A’s FIFO from X Condition to Y Condition, and clear data. • Change the packet B from Y Condition to X Condition. • Set frame number to frame register. •...
Page 265 TMP92CH21 Note: EPx_DATASETA,B change at 3 clocks of 12MHz after receiving SOF. Write data to FIFO after EPx_DATASETA,B are changing. EPx_DATASET_A EPx_DATASET_B EPx_DATASET EPx_BWR 3clocks (12MHz) DATA0 DATA0 DATA0 Figure 3.10.9 Isochronous transfer Mode 2009-06-19 92CH21-263...
Page 266 TMP92CH21 IDLE Receive SOF Clear X condition (A) Receive IN token without transmitting data Set FULL to STATUS Confirm Token packet • PID • Address • Endpoint • Transfer mode • Error Confirm Status Invalid • Confirm STATUS register (status) Generate DATA PID •...
Page 267 TMP92CH21 (d-2) Isochronous receiving mode Transaction format for Isochronous transfer type in receiving is given below. • Token: OUT • Data: DATA0 Control flow Isochronous transfer type is frame management. And data that is written to FIFO by OUT token is received to the CPU in the next frame. Below are two conditions in FIFO of Isochronous receiving mode transferring X.
Page 268 TMP92CH21 In renewed frame, Packet A’s FIFO interchanges with packet B’s FIFO, and the transaction uses the same flow. If SOF token is not received by error and so on, this data is lost because the frame is not renewed. There is no problem in receiving PID and if frame data is received with CRC error, USB sets LOST to STATUS on FRAME register, and exact frame number is unknown.
Page 269 TMP92CH21 IDLE Receive SOF Clear X Condition (A) Receive OUT token without transmitting data Set FULL to STATUS Confirm Token packet • PID • Address • Endpoint • Transfer mode • Error Invalid Confirm Status Confirming STATUS register (status) Confirm DATA PID Error, time out exept data PID •...
Page 270 TMP92CH21 3.10.7 Bus Interface and Access to FIFO (1) CPU bus interface The UDC prepares two types of FIFO access, single packet and dual packet. In single packet mode, FIFO capacity that is implemented by hardware is used as large FIFO. In dual packet mode, FIFO capacity is divided into two and used as two FIFOs.
Page 271 TMP92CH21 (a) Single packet mode This is data sequence of single packet mode when CPU bus interface is used. Figure 3.10.13 is receiving sequence. Figure 3.10.14 is transmitting sequence. This chapter focuses on access to FIFO. For Data sequence with USB host refer to chapter 5.
Page 272 TMP92CH21 Below is the transmitting sequence in single packet mode. Wait transmission event IDLE Transmission event DATASET register • Check bit of EPx_DSET_A Distinction transmitting number Transmitting number ≤ payload Transmitting number > payload • Write payload number in relevant endpoint •...
Page 273 TMP92CH21 (b) Dual packet mode In dual packet mode, FIFO is divided into A and B packet, and is controlled according to priority in hardware. It can be performed at once, transmitting and receiving data to USB host and exchanges to external of UDC. When it reads out data from FIFO for receiving, confirm condition of two packets, and consider the order of priority.
Page 274 TMP92CH21 Data can be set to available FIFO when transmitting regardless of packet A or B. Below is the Transmitting Sequence in Dual Packet Mode. Wait transmitting event IDLE Transmitting event DATASETregister • Check bit of EPx_DSET_A • Check bit of EPx_DSET_B Transmittind data distinction Transmitting number <...
Page 275 TMP92CH21 (c) Issuance of NULL packet If transmitting NULL packet, by input L pulse from EPx_EOPB signal, data of 0 length is set to FIFO, and NULL packet can be transferred to IN token. But if NULL data is set to FIFO, it is valid only in the case where SET signal is L level condition (where FIFO is empty).
Page 276 TMP92CH21 3.10.8 USB Device answer The USB controller (UDC) sets various registers and initialization in the UDC in detecting of hardware reset, detecting of USB bus reset, and enumeration answer. Each condition is explained below. (1) Bus reset detect condition. When the UDC detects a bus reset on the USB signal line, it initializes internal register, and it prepares enumeration operation from USB host.
Page 277 TMP92CH21 ISO transfer mode Below is the transfer condition for the previous frame. Receiving SOF renews this. OUT (RX) IN (TX) Initial READY READY Not transfer READY FULL Finish normally DATAIN READY Detect anerror RXERR TXERR Transfer modes other than ISO transfer This is the result of the previous transfer.
Page 278 TMP92CH21 3.10.9 Power Management USB controller (UDC) can be switched from optional resume condition (turn on the power supply condition) to suspend (Suspension) condition, and it can be returned from suspend condition to turn on the power supply condition. This function can be set to low electricity consumption by operating CLK supplying for UDC.
Page 279 TMP92CH21 (4) Low power consumption by control of CLK input signal When the UDC switches to suspend condition, it stops CLK and switches to low power consumption condition. But as system, this function enables low power consumption by stopping source of CLK. CLK that is supplied to the UDC can be controlled using USBINTFR1<INT_SUS>,...
Page 280 TMP92CH21 • Return from suspend condition by USB reset (by INT_CLKON interrupt) When UDC stops CLK in suspend condition, UDC can not detect USB reset and control CLK in suspend condition as above mentioned. In case CLK is stopped in suspend condition, UDC can detect USB reset and return from suspend condition by supplying CLK (USBCR1<USBCLKE>=1) after detecting INT_CLKON interrupt.
Page 281 TMP92CH21 3.10.10 Supplement (1) External access flow to USB communication Normal movement SETUP DATA0 ACK DATA1 DATA0 DATA1 INT_SETUP INT_ ENDPOINT0 INT_STATUS REQUEST FLAG EP0 FIFO access Request access Setup Received access EOP register access Stage error SETUP DATA0 ACK DATA1 DATA0 SETUP...
Page 282 TMP92CH21 (2) Register initial value Initial Value Initial Value Register Name Beginning Value Register Name Initial Value OUTSIDE Reset USB_RESET OUTSIDE Reset USB_RESET bmRequestType 0x00 0x00 INT control 0x00 0x00 bRequest 0x00 0x00 USBBUFF_TEST 0x00 Hold wValue_L 0x00 0x00 USB state 0x01 0x01 wValue_H...
Page 283 TMP92CH21 (3) USB control flow chart (a) Transaction for standard request (Outline flowchart (Example)) USB interrupt Call USBINT0 function Evaluate Interrupt SETUP ENDPOINT 0 STATUS STATUS NAK ENDPOINT 1 transaction transaction transaction transaction transaction 2009-06-19 92CH21-281...
Page 284 TMP92CH21 (b) Condition change Turn on power supply Initialization transaction Normal finish/No transaction Waiting USB interrupt condition Transmit Request error/STALL Receive USB token Transaction error/ Transmit STALL Request transaction condition 2009-06-19 92CH21-282...
Page 285 TMP92CH21 (c) Device request and evaluation of various requests Start Get request data Evaluate Request Standard request Class request Vendor request Error transaction * Error for not CLEAR_FEATURE * Error for not support support SET_FEATURE GET_STATUS SET_ADDRESS SET_CONFIGURATION GET_CONFIGURATION SET_INTERFACE GET_INTERFACE SYNCH_FRAME GET_DESCRIPTOR...
Page 286 TMP92CH21 (c-1) CLEAR_FEATURE request transaction Start Is request right？ Evaluate Recipient Device Endpoint Error transaction Disable remote Clear stall setting wakeup setting Finish transaction 2009-06-19 92CH21-284...
Page 287 TMP92CH21 (c-2) SET_FEATURE request transaction Start Is request right? Evaluate Recipient Device Endpoint Error transaction Enable remote Set stall wakeup setting Finish transaction 2009-06-19 92CH21-285...
Page 288 TMP92CH21 (c-3) GET_STATUS request transaction Start Is request right? Evaluate Recipient Device Interface Endpoint Error transaction Set self power Set 0 x 0 0 data of Set stall information supply information 2 bytes Finish transaction 2009-06-19 92CH21-286...
Page 289 TMP92CH21 (c-4) SET_CONFIGRATION request transaction Start Is request right？ Is EP0 stall？ Is assignment value valid？ Is state valid？ Set assigned configuration Error transaction value Clear stall flag Finish transaction 2009-06-19 92CH21-287...
Page 290 TMP92CH21 (c-5) GET_CONFIGRATION request transaction Start Is request right? Is state valid? Set present configuraion Error transaction value Finish transaction 2009-06-19 92CH21-288...
Page 291 TMP92CH21 (c-6) SET_INTERFACE request transaction Start Is request right? Is EP0 stall? Is assigned value valid? Is state valid? Set each endpoint to Error transaction assigned configuration value. Finish transaction 2009-06-19 92CH21-289...
Page 292 TMP92CH21 (c-7) SYNCH_FRAME request transaction Start Is request right? Is EP0 stall? Is assigned value valid? Is state valid? Set alternate setting value Error transaction to present transmitting data. Finish transaction 2009-06-19 92CH21-290...
Page 293 TMP92CH21 (c-8) SYNCH_FRAME request transaction Start Is request right? Error transaction Finish transaction (c-9) SET_DESCRIPTOR request transaction Start Is request right? Error transaction Finish transaction 2009-06-19 92CH21-291...
Page 294 TMP92CH21 (c-10) GET_DESCRIPTOR request transaction Start Is request right? Is EP0 stall? Is assigned value valid? Is state valid? Config String Device Error transaction Set device Set config Set string descriptor descriptor descriptor information. information. information. Write information to FIFO[EP0_fifowrite ( )] 2009-06-19 92CH21-292...
Page 295 TMP92CH21 (c-11) Data read transaction to FIFO by EP0 Start Is request right? Stage information = data stage Read data from FIFO STATUS_NAK interrupt disable STATUS_NAK interrupt enable Stage information = status stage Data read from FIFO All data number Finish transaction renew transfer address 2009-06-19...
Page 296 TMP92CH21 (c-12) Data write transaction to FIFO by EP0 Start Is request right? Set transmitting size to SIZE register Stage information = data stage Write data to FIFO STATUS_NAK interrupt enable Is data number a multiple of payload size? Set data size to SIZE register STATUS_ NAK interrupt disable Write data to FIFO Stage information = status stage...
Page 297 TMP92CH21 (c-13) Initial setting transaction of microcontroller Start Interrupt disable Set Stack point Set Various interrupts Clear vRAM UDC initialization[UDC_INIT] USB firmware initialization[USB_INIT] Interrupt enable Main transaction[main ( )] (c-14) Initial setting transaction of UDC Start USBC reset transaction 2009-06-19 92CH21-295...
Page 298 TMP92CH21 (c-15) Initial transaction of USB number changing firmware Start Renew stage information Renew current information Renew support information Invalid EP except EP0 Various flag Intialization (c-16) Set DEVICE_ID data to DEVICE_ID of UDC Start Set DEVICE_ID data to DEVICE_ID_RAM area. 2009-06-19 92CH21-296...
Page 299 TMP92CH21 (c-17) Descriptor data set transaction Start Set descriptor data to DESC_RAM area. (c-18) USB interrupt transaction Start Read INT register Evaluate Interrupt Setup interrupt Endpoint 0 interrupt Status_NAK interrupt Status_interrupt Others transaction [Proc_ ENDPOINT] [Proc_STATUSNAKINT] [Proc_STATUSINT] Error transaction [Proc_SETUPINT] Evaluate Request transaction [STATUS_judge] 2009-06-19...
Page 300 TMP92CH21 (c-19) Dummy function for not using maskable interrupts. • Transaction performs nothing, therefore outline flow is skipped. (c-20) Request evaluation transaction. If transaction result is error, it initiates STALL command. Start Is request right? Error transaction (c-21) SETUP stage transaction Start Is request right? Stage information = SETUP stage...
Page 301 TMP92CH21 (c-22) Perform endpoint 0 transaction except in SETUP stage. Start Evaluate Stage Data stage Status stage Others GET system request Finish normally Error transaction [EP0_fifowrite] SET system request [EP0_fiforead] (c-23) Status stage interrupt transaction Start Status stage? Normal finish transaction Error transaction 2009-06-19...
Page 302 TMP92CH21 (c-24) STATUS_NAK interrupt transaction Start Data stage? Normal finish Error transaction transaction (c-25) This transaction is a non-transaction for USB interrupts. Start 2009-06-19 92CH21-300...
Page 303 TMP92CH21 (c-26) Getting descriptor information (related to standard request) Start Get device information on descriptor Is config within support? Get config information on descriptor Interface is within support in config present. Get device information on descriptor Increment count to next config information 2009-06-19 92CH21-301...
Page 304 TMP92CH21 3.10.11 Notice and Restrictions Limitation of writing to COMMAND register in special timing When “STALL” command is issued, ENDPOINT status might shift to “INVALID”. To avoid this problem, follow the routine below. BULK (IN/OUT) When issuing a STALL command to endpoint in BULK transfer, be sure to issue STALL command after stopping RD/WR access to endpoint;...
Page 305 TMP92CH21 When generating toggle error of device controller UDC operation If USB host fails to receive ACK transmitted from the UDC in OUT transfer, the USB host transmits the same data to the UDC again. When the FIFO is available to receive, the UDC detects toggle error because of detecting the same data(having the same toggle as the data which is received just before) and returns ACK.
Page 306 TMP92CH21 3.11 Analog/Digital Converter The TMP92CH21 incorporates a 10-bit successive approximation type analog/digital converter (AD converter) with 4-channel analog input. Figure 3.11.1 is a block diagram of the AD converter. The 4-channel analog input pins (AN0 to AN3) are shared with the input only port G so they can be used as an input port. Note: When IDLE2, IDLE1 or STOP mode is selected, in order to reduce power consumption, the system may enter a stand-by mode with some timings even though the internal comparator is still enabled.
Page 307 TMP92CH21 3.11.1 Analog/Digital Converter Registers The AD converter is controlled by the three AD mode control registers: ADMOD0, ADMOD1 and ADMOD2. The four AD conversion data result registers (ADREG0H/L to ADREG3H/L) store the results of AD conversion. Figure 3.11.2 shows the registers related to the AD converter. AD Mode Control Register 0 −...
Page 308 TMP92CH21 AD Mode Control Register 1 − − − − ADMOD1 Bit symbol VREFON I2AD ADCH1 ADCH0 (12B9H) Read/Write Reset State Function VREF IDLE2 Always Always Always Always Analog input channel application write “0” write “0” write “0” write “0” selection 0: Stop control...
Page 309 TMP92CH21 AD Conversion Result Register 0 Low ADREG0L Bit symbol ADR01 ADR00 ADR0RF (12A0H) Read/Write Reset State Undefined AD conversion Function Stores lower 2 bits of data storage flag AD conversion result. 1: Conversion result stored AD Conversion Result Register 0 High ADREG0H Bit symbol ADR09...
Page 310 TMP92CH21 AD Conversion Result Register 2 Low ADREG2L Bit symbol ADR21 ADR20 ADR2RF (12A4H) Read/Write Reset State Undefined AD conversion Function Stores lower 2 bits of data storage flag AD conversion result. 1: Conversion result stored AD Conversion Result Register 2 High ADREG2H Bit symbol ADR29...
Page 311 TMP92CH21 3.11.2 Description of Operation (1) Analog reference voltage A high level analog reference voltage is applied to the VREFH pin; a low level analog reference voltage is applied to the VREFL pin. To perform AD conversion, the reference voltage, the difference between VREFH and VREFL, is divided by 1024 using string resistance.
Page 312 TMP92CH21 (3) Starting AD conversion To start AD conversion, write a 1 to ADMOD0<ADS> in AD mode control register “0” or ADMOD2<ADTRGE> in AD mode control register 2, and input falling edge on pin. When AD conversion starts, AD conversion busy flag ADTRG ADMOD0<ADBF>...
Page 313 TMP92CH21 Channel fixed repeat conversion mode Setting ADMOD0<REPEAT> and ADMOD0<SCAN> to 10 selects conversion channel fixed repeat conversion mode. In this mode, data on one specified channel is converted repeatedly. When conversion been completed, ADMOD0<EOCF> ADMOD0<ADBF> is not cleared to 0 but held at 1. INTAD interrupt request generation timing is determined by the setting of ADMOD0<ITM0>.
Page 314 TMP92CH21 (5) AD conversion time 132 states (6.6 μs at f = 20 MHz) are required for the AD conversion of one channel. (6) Storing and reading the results of AD conversion The AD conversion data upper and lower registers (ADREG0H/L to ADREG3H/L) store the results of AD conversion.
Page 315 TMP92CH21 Setting example: 1. Convert the analog input voltage on the AN3 pin and write the result to memory address 2800H using the AD interrupt (INTAD) processing routine. Main routine: ← 1 − − − − INTE0AD Enable INTAD and set it to interrupt level 4. ←...
Page 316 TMP92CH21 3.12 Watchdog Timer (Runaway detection timer) The TMP92CH21 contains a watchdog timer of runaway detecting. The watchdog timer (WDT) is used to return the CPU to the normal state when it detects that the CPU has started to malfunction (runaway) due to causes such as noise. When the watchdog timer detects a malfunction, it generates a non-maskable interrupt INTWD to notify the CPU of the malfunction.
Page 317 TMP92CH21 3.12.2 Operation The watchdog timer generates an INTWD interrupt when the detection time set in the WDMOD<WDTP1:0> has elapsed. The watchdog timer must be cleared to zero in software before an INTWD interrupt will be generated. If the CPU malfunctions (e.g., if runaway occurs) due to causes such as noise, but does not execute the instruction used to clear the binary counter, the binary counter will overflow and an INTWD interrupt will be generated.
Page 318 TMP92CH21 3.12.3 Control Registers The watchdog timer (WDT) is controlled by two control registers WDMOD and WDCR. (1) Watchdog timer mode register (WDMOD) Setting the detection time for the watchdog timer in <WDTP1:0> This 2-bit register is used for setting the watchdog timer interrupt time used when detecting runaway.
Page 319 TMP92CH21 − − WDMOD Bit symbol WDTE WDTP1 WDTP0 I2WDT RESCR (1300H) Read/Write Reset State Function WDT control Select detecting time Always IDLE2 1: Internally Always write “0” connects write “0” 1: Enable 00: 2 0: Stop WDT out 01: 2 1: Operate to the 10: 2...
Page 320 TMP92CH21 3.13 Real Time Clock (RTC) 3.13.1 Function Description for RTC Clock function (hour, minute, second) Calendar function (month and day, day of the week, and leap year) 24- or 12-hour (AM/PM) clock function +/−30 s adjustment function (by software) Alarm function (alarm output) Alarm interrupt generate 3.13.2...
Page 321 TMP92CH21 3.13.3 Control Registers Table 3.13.1 PAGE 0 (Clock function) Registers Symbol Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Function Read/Write SECR 1320H 40 sec 20 sec 10 sec 8 sec 4 sec 2 sec 1 sec Second column MINR 1321H 40 min...
Page 322 TMP92CH21 3.13.4 Detailed Explanation of Control Register RTC is not initialized by system reset. Therefore, all registers must be initialized at the beginning of the program. (1) Second column register (for PAGE0 only) SECR Bit symbol (1320H) Read/Write Reset State Undefined Function "0"...
Page 323 TMP92CH21 (2) Minute column register (for PAGE0/1) MINR Bit symbol (1321H) Read/Write Reset State Undefined Function “0” is read. 40 min 20 min 10 min 8 min 4 min 2 min 1 min column column column column column column column 0 min 1 min 2 min...
Page 324 TMP92CH21 (3) Hour column register (for PAGE0/1) In 24-hour clock mode (MONTHR<MO0> = “1”) HOURR Bit symbol (1322H) Read/Write Reset State Undefined Function “0” is read. 20 hours 10 hours 8 hours 4 hours 2 hours 1 hour column column column column column...
Page 325 TMP92CH21 (4) Day of the week column register (for PAGE0/1) DAYR Bit symbol (1323H) Read/Write Reset State Undefined Function “0” is read. Sunday Monday Tuesday Wednesday Thursday Friday Saturday Note: Do not set data other than as shown above. (5) Day column register (PAGE0/1) DATER Bit symbol (1324H)
Page 326 TMP92CH21 (6) Month column register (for PAGE0 only) MONTHR Bit symbol (1325H) Read/Write Reset State Undefined Function “0” is read. 10 months 8 months 4 months 2 months 1 month January February March April June July August September October November December Note: Do not set data other than as shown above.
Page 327 TMP92CH21 (8) Year column register (for PAGE0 only) YEARR Bit symbol (1326H) Read/Write Reset State Undefined Function 80 years 40 years 20 years 10 years 8 years 4 years 2 years 1 year 00 years 01 years 02 years 03 years 04 years 05 years 99 years...
Page 328 TMP92CH21 (10) Setting PAGE register (for PAGE0/1) PAGER Bit symbol INTENA ADJUST ENATMR ENAALM PAGE (1327H) Read/Write Reset State Undefined Undefined Undefined Function INTRTC 0: Don’t Clock ALARM PAGE Read-modify-write care selection instruction is 0: Disable “0” is read. 0: Disable 0: Disable “0”...
Page 329 TMP92CH21 3.13.5 Operational description (1) Reading clock data 1. Using 1Hz interrupt 1Hz interrupt and the count up of internal data synchronize. Therefore, data can read correctly if reading data after 1Hz interrupt occurred. 2. Using two times reading There is a possibility of incorrect clock data reading when the internal counter carries over.
Page 330 TMP92CH21 (2) Writing clock data When a carry over occurs during a write operation, the data cannot be written correctly. Please use the following method to ensure data is written correctly. 1. Using 1Hz interrupt 1Hz interrupt and the count up of internal data synchronize. Therefore, data can write correctly if writing data after 1Hz interrupt occurred.
Page 331 TMP92CH21 Disabling the clock A clock carry over is prohibited when “0” is written to PAGER<ENATMR> in order to prevent malfunction caused by the Carry hold circuit. While the clock is prohibited, the Carry hold circuit holds a one sec. carry signal from a divider. When the clock becomes enabled, the carry signal is output to the clock, the time is revised and operation continues.
Page 332 TMP92CH21 3.13.6 Explanation of the interrupt signal and alarm signal The alarm function used by setting the PAGE1 register and outputting either of the following three signals from ALARM pin by writing “1” to PAGER<PAGE>. INTRTC outputs a 1-shot pulse when the falling edge is detected. RTC is not initialized by RESET. Therefore, when the clock or alarm function is used, clear interrupt request flag in INTC (interrupt controller).
Page 333 TMP92CH21 3.14 LCD Controller This LSI incorporates two types of liquid crystal display driving circuit for controlling LCDs. One circuit supports an internal RAM LCD driver that can store display data in the LCD driver itself, and the other circuit supports a shift-register type LCD driver that must serially transfer the display data to the LCD driver for each display picture.
Page 334 TMP92CH21 3.14.1 LCDC features by Mode The various features and pin operations of are as follows. Table 3.14.1 LCDC features by Mode (example: T6C13B, T6B66A by Toshiba) Shift Register Type LCD Driver Control Mode RAM Built-in Type LCD driver LCD Driver Control...
Page 335 TMP92CH21 3.14.2 SFRs LCDMODE0 Register LCDMODE0 Bit symbol RAMTYPE1 RAMTYPE0 SCPW1 SCPW0 MODE3 MODE2 MODE1 MODE0 (0280H) Read/Write Reset State Function Display RAM LD bus transmission Mode setting speed 0000: Built-in RAM type 0101: STN 8 bpp (256 colors) 00: Reserved 00: Internal SRAM 0001: SR 1 bpp 0110: STN 12 bpp (4 K colors)
Page 336 TMP92CH21 LCD Size Setting Register LCDSIZE Bit symbol COM3 COM2 COM1 COM0 SEG3 SEG2 SEG1 SEG0 (0284H) Read/Write Reset State Function Common setting Segment setting 0000: Reserved 0101: 200 0000: Reserved 0101: 320 0001: 64 0110: 240 0001: 64 0110: 480 0010: 120 0111: 320 0010: 128...
Page 337 TMP92CH21 LCD Clock Counter Register 0 LCDCCR0 Bit symbol PCPV2 PCPV1 PCPV0 (0288H) Read/Write Reset State Function Pre LCP1 CLK: LCP1 pulse number Dummy clock number until valid clock of gate driver LCP1 LCD Clock Counter Register 1 LCDCCR1 Bit symbol TLDE4 TLDE3 TLDE2...
Page 338 TMP92CH21 LCD RED Palette Register LCDRP10 Bit symbol (0291H) Read/Write Reset State Function 256-color STN mode 256-color STN mode RED1 level setting RED0 level setting LCDRP32 Bit symbol (0292H) Read/Write Reset State Function 256-color STN mode 256-color STN mode RED3 level setting RED2 level setting LCDRP54 Bit symbol...
Page 339 TMP92CH21 LCD Green Palette Register LCDGP10 Bit symbol (0295H) Read/Write Reset State Function 256-color STN mode 256-color STN mode GREEN1 level setting GREEN0 level setting LCDGP32 Bit symbol (0296H) Read/Write Reset State Function 256-color STN mode 256-color STN mode GREEN3 level setting GREEN2 level setting LCDGP54 Bit symbol...
Page 340 TMP92CH21 LCD OE0 Control Register LCDOE00 Bit symbol OE007 OE006 OE005 OE004 OE003 OE002 OE001 OE000 (02B0H) Read/Write Reset State Function OE0 control of TFT panel gate driver LCDOE01 (02B1H) LCDOE04 (02B4H) LCDOE05 Bit symbol OE057 OE056 OE055 OE054 OE053 OE052 OE051 OE050...
Page 341 TMP92CH21 Start Address Register Row Number Setting Register − (Bit23 to 16) (Bit15 to 8) (Bit7 to 1) (Bit8) (Bit7 to 0) LSARAH LSARAM LSARAL CMNAH CMNAL − A area (02A2H) (02A1H) (02A0H) (02A4H) (02A3H) LSARBH LSARBM LSARBL CMNBH CMNBL −...
Page 342 TMP92CH21 3.14.3 Shift Register Type LCD Driver Control Mode (SR mode and STN color) 3.14.3.1 Description of Operation Set the mode of operation, start address of source data save memory, grayscale level and LCD size to control registers before setting start register. After setting start register, the LCDC outputs a bus release request to the CPU and reads data from source memory.
Page 343 TMP92CH21 3.14.3.2 Memory Space (Common spec. SR mode and TFT mode) The LCDC can display an LCD panel image which is divided horizontally into 3 parts; upper, middle and lower. Each area is called A area, B area and C area with the characteristics shown below.
Page 344 TMP92CH21 3.14.3.3 Display Memory Mapping and Panning Function (Common spec. SR mode and TFT mode) The LCDC can only change the panel window if you change each start address of A, B and C areas. The display area can be panned vertically and horizontally by changing the row address and column address.
Page 345 TMP92CH21 • Monochrome: 1 bpp (bit per pixel) Display memory image Address 0 Address 1 Address 2 Address 3 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 LD bus output sequence 4-bit width A type 4-bit width B type...
Page 346 TMP92CH21 • 8/16 grayscales (4 bpp: 8 grayscales case, valid data is 3 bits but data space needs 4 bits) Display memory image Address 0 Address 1 Address 2 Address 3 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 1 pixel Address 4 Address 5...
Page 347 TMP92CH21 • 256 colors (8 bpp; R: 3 bits, G: 3 bits, B: 2 bits) Display memory image Address 0 Address 1 Address 2 Address 3 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Address 4 Address 5 Address 6...
Page 348 TMP92CH21 • 4096 colors (12 bpp: R: 4 bits, G: 4 bits, B: 4 bits) Display memory image Address 0 Address 1 Address 2 Address 3 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Address 4 Address 5 Address 6...
Page 349 TMP92CH21 3.14.3.5 Refresh Rate Setting Frame cycle (refresh rate) is generated from setting of LSCC (LCDSCC<SCC7:0>) and FP [9:0] (LCDCTL0<FP9, 8>, LCDFFP<FP7:0>). The LBCD terminal outputs one pulse every cycle and the LFR normally outputs an inverted signal every cycle. But when the DIVIDE FRAME function is used, the LFR signal changes to a special signal for high quality display.
Page 350 TMP92CH21 (2) Refresh rate adjust function (Correct function) In this function, the LBCD frequency: refresh rate is generated by setting LCDSCC<SCC7:0> and FP [9:0] register. The FFP value is normally set at the same value as the ROW number, but this value can be used for correction of BCD frequency: refresh rate.
Page 351 TMP92CH21 (3) Divide frame adjust function The DIVIDE FRAME function allows for adjustments to reduce uneven display in large LCD panels. When this function is enabled by setting <FRMON> = 1, the LFR signal alternates between high and low level with each LLP cycle for the LCDDVM register values given below.
Page 352 TMP92CH21 = 78.02 Hz (at <FP9:0> = 120) 1-picture display time LBCD LD7 to LD0 (8-bit case) Use internal signal Data transmission to CPU (Interrupt) (1 row data) Figure 3.14.6 Whole Timing Diagram of SR Mode : LLP cycle LBCD : CPU opration time : Stop time STOP...
Page 353 TMP92CH21 3.14.3.6 LCD Data Transmission Speed and Data Bus Occupation Rate After setting start register, the LCDC outputs a bus release request to the CPU and reads data from source memory. The LCDC then transmits LCD size data to the external LCD driver through the special LCDC data bus (LD11 to LD0). At this time, the control signals connected to the LCD driver output the specified waveform which is synchronized with the data transmission.
Page 354 TMP92CH21 3.14.3.7 Timing Diagram of LD Bus The TMP92CH21 can select to display RAM for external SRAM: Available to set WAIT, internal SRAM and external SDRAM: 16, 32, 64, 128, 256 and 512 Mbits. As a 480-byte FIFO buffer is built into this LCDC, the LD bus speed can be controlled.
Page 355 TMP92CH21 Internal system clock A23 to A0 N + 1 N + 2 N + 3 N + 4 N + 5 D32 to D0 or D15 to D0 IN + 1 IN + 2 IN + 3 IN + 4 IN + 5 8-bit bus LCP0 (2CP)
Page 356 TMP92CH21 A23 to A0 Column D31 to D0 or D16 to D0 IN + 1 IN + 2 IN + 3 IN + 4 IN + 5 IN + 6 IN +7 8-bit bus 16-bit bus, monochrome LCP0 (2CP) /4 grayscales/256 colors 32-bit bus, monochrome LD7 to LD0 OUT + 1 OUT + 2 OUT + 3 OUT + 4...
Page 357 TMP92CH21 3.14.3.8 Setting of Color Palette This LSI can support monochrome, 4-, 8-, 16-level grayscales and color STN panels, and color TFT panels. The following shows the settings for each mode. • Monochrome No need for special setting, simply select monochrome mode by LCDMODE1<MODE3:0>...
Page 358 TMP92CH21 • 4096 colors STN STN4096 color mode is selected by LCDMODE1<MODE3:0>. This LCDC has a maximum 4096-color palette. If STN4096 color mode is selected, individual color contrast levels cannot be adjusted. 2009-06-19 92CH21-356...
Page 359 TMP92CH21 3.14.3.9 Example of SR Type LCD driver connection COM001 × 240 commons 80 segments LCD (Color) COM240 T6C13B (240-row driver selection) TMP92CH21 O001 COM001 TEST DI7 to DI0 × 240 commons 240 segments DUAL LCD (Monochrome) VCCL/R, V0L/R, V1L/R, V4L/R, V5L/R O240 COM240...
Page 360 TMP92CH21 3.14.3.10 Program Example (4 K colors STN) ; ********PORT settings ********* (PLFC), 0ffh ; LD7 to LD0 set (PLCR), 0f0h ; Output mode (PKFC), 0fh ; LBCD, LLP, LCP0 ; ********LCD settings********* (LCDSCC), 51 ; Counter set (Refresh rate: 100 Hz at fc = 40 MHz) (LCDCCR0), 01h (LCDCCR1), 01h ;...
Page 361 TMP92CH21 3.14.4 TFT Color Display Mode 3.14.4.1 Description of Operation This is basically the same setting as for SR mode. Set the mode of operation, start address of source data save memory, color level and LCD size to control registers before setting start register. After setting start register, the LCDC outputs a bus release request to the CPU and reads data from source memory.
Page 362 TMP92CH21 Relation of memory map image and output data • 256 colors (8 bpp; R: 3 bits, G: 3 bits, B: 2 bits) Display memory image Address 0 Address 1 Address 2 Address 3 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Address 4 Address 5 Address 6...
Page 363 TMP92CH21 Relation of memory map image and output data • 4096 colors (12 bpp; R: 4 bits, G: 4 bits, B: 4 bits) Display memory image Address 0 Address 1 Address 2 Address 3 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Address 4 Address 5 Address 6...
Page 364 TMP92CH21 3.14.4.5 Setting Each Control Signals The TFT source driver is controlled by base clock (LCP0), data start clock (LFR) and load pulse (LLP). Special data bus LD11 to LD0 uses 8 bits or 12 bits for suitable LCD driver. The timing of each signal can be finely adjusted using the relevant control register.
Page 365 TMP92CH21 LCD Clock Counter Register 0 LCDCCR0 Bit symbol PCPV2 PCPV1 PCPV0 (0288H) Read/Write Reset State Function Pre LCP1 CLK: LCP1 pulse number Dummy clock number until valid clock of gate driver LCP1 Delay control 1 is set by LCDCCR0<PCPV2:0>. Delay of Dummy clock is controlled by pulse number derived by subtracting common number and <PCPV2:0>...
Page 366 TMP92CH21 3.14.5 Source Driver Control Data shift clock; LCP0, Data; LD11 to LD0 and LLP signals become valid after the time (offset time + set up time set in (LCDCCR1)) from LCP1. LLP signal has 2 modes; Mode1 (LLP rises 1 LCP0 clock before valid data) and Mode2 (LLP rises at the same time as valid data) 1.
Page 367 TMP92CH21 3.14.5.1 Gate Driver Control The TFT gate driver is controlled bybase clock LCP1and vertical shift data signal LBCD. This LSI has 3-bit output enable signals LGOE2 to LGOE0which can be controlled individually. The TFT gate driver’s output can be controlled by this timing and is available for blanking adjustment and zoom function.
Page 368 TMP92CH21 (Notes on settings) 1. LCP0 cycle: LCP0=f × n (n=2, 4, 8: transmission speed of LD bus) LCP0 cycle is generated by system clock and value of LCDMODE0<SCPW1:0> 2. LCP1 cycle: LCP1= f × 16 × (SCC + 1) LCP1 cycle is generated by value of LCDSCC register.
Page 369 TMP92CH21 4. LLP Setting: Set up time is determined by LCDCCR1. Set up time of LLP (horizontal front porch) is set in LCDCCR1 register. This is called “Delay control 2”. 1 pulse of this set up time in LCDCCR1 register is equal to 8 times of fsys regardless of LCP0 and LCP1.
Page 370 TMP92CH21 7. LGOE0 to 2: Programmable waveform LGOE0 is output on the rising edge of the first LCP1 and repeats every 3 pulses of LCP1. LGOE1 is the 2nd LCP1 and LGOE2 the 3rd, and they also repeat every 3 pulses of LCP1.
Page 371 TMP92CH21 3.14.5.2 Example of TFT LCD driver connection JBT6L78-AS (162-gate driver) TMP92CH21 TEST1 TEST2 160 SEG × 3 (RGB) × 162 COM OE3 to OE1 LGOE2 to LGOE0 G162 G162 LBCD LCP0 LOAD LOAD Open DI/O DO/I LCP1 DO/I DI/O LD11 to LD0 DA5 to DA2 DA5 to 2...
Page 372 TMP92CH21 3.14.5.3 Program sample (4K color TFT) ; ********PORT settings ********* (PACR), 78h ; LD11-LD8 set (PLFC), 0ffh ; LD7-LD0 set (PLCR), 0f0h Output mode (PKFC), 0bh LBCD, LLP, LCP0 (PCCR), 0c0h PC6: LDIV (for TFT) PC7: LCP1 (PCFC), 0c0h PC6: LDIV ;...
Page 373 TMP92CH21 3.14.6 Built-in RAM Type LCD driver Mode 3.14.6.1 Description of Operation Data transmission to the LCD driver is executed by a transmit instruction from the CPU. After setting operation mode of to the control register, when a CPU transmit instruction is executed the LCDC outputs a chip select signal to the LCD driver connected externally by the control pin (LCP0...).
Page 374 TMP92CH21 3.14.6.3 Sequential Access Type Data transmission to the LCD driver is executed by a transmit instruction from the CPU. After setting operation mode to the control register, when a CPU transmit instruction is executed the LCDC outputs a chip select signal to the LCD driver connected externally by the control pin (LCP0...).
Page 375 TMP92CH21 3.14.6.4 Example of Built-in RAM LCD driver connection T6B66A TMP92CH21 (65-row driver) COM001 COM001 65 COM × 80 SEG VLC1, VLC2, VLC3, VLC4, VLC5 COM065 COM065 LCP0 DB0 to DB7 D0 to D7 EIO1 Open EIO2 T6B65A (80-column driver) Note: Other circuit is required for power supply for LCD driver display.
Page 376 TMP92CH21 3.14.6.5 Program Example • Setting example: when using 80 segments × 65 commons LCD driver. Assign external column driver to LCDC1 and row driver to LCDC4. This example uses LD instruction in setting of instruction and micro DMA burst function for soft start in setting of display data.
Page 377 TMP92CH21 3.15 Melody/Alarm Generator (MLD) The TMP92CH21 contains a melody function and alarm function, both of which are output from the MLDALM pin. Five kinds of fixed cycle interrupt are generated using a 15-bit counter for use as the alarm generator. The features are as follows.
Page 378 TMP92CH21 3.15.1 Block Diagram Reset Internal data bus [Melody Generator] MELFH, MELFL register MELOUT MELFH Invert <MELON> Comparator (CP0) Stop and clear Clear Low-speed 12-bit counter (UC0) clock INTALM0 (8192 Hz) INTALM1 (512 Hz) Edge detector INTALM2 (64 Hz) INTALM3 (2 Hz) INTALM4 (1 Hz) 15-bit counter (UC1) INTALMH...
Page 379 TMP92CH21 3.15.2 Control Registers ALM Register Bit symbol (1330H) Read/Write Reset State Function Setting alarm pattern MELALMC Register − − − − MELALMC Bit symbol ALMINV MELALM (1331H) Read/Write Reset State Function Free-run counter control Alarm Output 00: Hold waveform waveform invert 01: Restart...
Page 380 TMP92CH21 3.15.3 Operational description 3.15.3.1 Melody Generator The Melody function generates signals of any frequency (4 Hz to 5461 Hz) based on a low-speed clock (32.768 kHz) and outputs the signals from the MLDALM pin. The melody tone can easily be heard by connecting an external loud speaker. (Operation) MELALMC<MELALM>...
Page 381 TMP92CH21 3.15.3.2 Alarm Generator The alarm function generates eight kinds of alarm waveform having a modulation frequency of 4096 Hz determined by the low-speed clock (32.768 kHz). This waveform is reversible by setting a value to a register. The alarm tone can easily be heard by connecting an external loud speaker. Five kinds of fixed cycle (interrupts can be generated 1 Hz, 2 Hz, 64 Hz, 512 Hz, 8 192 Hz) by using a counter which is used for the alarm generator.
Page 382 TMP92CH21 Example: Waveform of alarm pattern for each setting value (Not inverted) Modulation frequency AL1 pattern (4096 Hz) (Continuous output) AL2 pattern (8 times/1 s) 31.25 ms AL3 pattern (Once) 500 ms AL4 pattern (Twice/1 s) 62.5 ms AL5 pattern (3 times/1 s) 62.5 ms AL6 pattern...
Page 383 TMP92CH21 3.16 SDRAM Controller (SDRAMC) The TMP92CH21 includes an SDRAM controller which supports SDRAM access by CPU/LCDC. The features are as follows. (1) Support SDRAM Data rate type: Only SDR (Single data rate) type Bulk of memory: 16/64/128/256/512 Mbits Number of banks: 2/4 banks Width of data bus: 16/32...
Page 384 TMP92CH21 3.16.1 Control Registers Figure 3.16.1 shows the SDRAMC control registers. Setting these registers controls the operation of SDRAMC. SDRAM Access Control Register 1 − − SDACR1 Bit symbol SMRD SWRC SBST SBL1 SBL0 SMAC (0250H) Read/Write Reset State Function Always Always Mode...
Page 385 TMP92CH21 SDRAM Command Register SDCMM Bit symbol SCMM2 SCMM1 SCMM0 (0253H) Read/Write Reset State Function Command issue (Note 1) (Note 2) 000: Not execute 001: Initialization sequence a. Precharge All command b. Eight Auto Refresh commands c. Mode Register Set command 100: Mode Register Set command 101: Self Refresh Entry command 110: Self Refresh Exit command...
Page 386 TMP92CH21 3.16.2 Operation Description (1) Memory access control SDRAM controller is enabled when SDACR1<SMAC> = 1. And then SDRAM control signals ( SDCS , SDRAS , SDCAS , SDWE , SDLLDQM, SDLUDQM, SDULDQM, SDUUDQM, SDCLK and SDCKE) are operating during the time CPU or LCDC accesses CS1 or CS2 area.
Page 387 TMP92CH21 85 states (320-byte read) SDCLK SDCKE SDUUDQM SDULDQM SDLUDQM SDLLDQM SDCS SDRAS SDCAS SDWE A15 to A0 CA (n + 4) CA (n + 8) (n + 312) (n + 316) CA (n + 12) CA (n) D31 to D0 D (n + 4) D (n + 8) D (n + 12)
Page 388 TMP92CH21 (3) Refresh control This LSI supports two refresh commands: auto-refresh and self-refresh. (a) Auto-refresh The auto-refresh command is automatically generated at intervals set by SDRCR<SRS2:0> by setting SDRCR<SRC> to “1”. The generation interval can be = 20 MHz). set from between 47 to 312 states (2.4 μs to 15.6 μs at f CPU operation (instruction fetch and execution) stops while performing the auto-refresh command.
Page 389 TMP92CH21 (b) Self-refresh The self-refresh ENTRY command is generated by setting SDCMM<SCMM2:0> to “101”. The self-refresh cycle is shown in Figure 3.16.5. During self-refresh Entry, refresh is performed within the SDRAM (an auto-refresh command is not needed). The auto-refresh command is automatically executed once when self-refresh is released, following which, refresh is executed according to the setting of the auto- refresh command.
Page 390 TMP92CH21 (4) SDRAM initialize This LSI can generate the following SDRAM initialize routine after introduction of power supply to SDRAM. The command is shown in Figure 3.16.6. 1. Precharge all commnad 2. Eight Auto Refresh commands 3. Mode Register set command The above commands are issued by setting SDCMM<SCMM2:0>...
Page 391 TMP92CH21 (5) Connection example Figure 3.14.7-Figure 3.14.10 shows an example of connections between the TMP92CH21 and SDRAM Table 3.16.3 Connection with SDRAM SDRAM Pin Name Data Bus Width: 16 Bits Data Bus Width 32 Bits TMP92CH21 Pin Name 16 M 64 M 128 M 64 M...
Page 392 TMP92CH21 TMP92CH21 SDCLK SDCKE A11 to A0 A11 to A0 D15 to D0 D15 to D0 D31 to D16 SDRAS SDCAS SDWE SDCS SDLUDQM UDQM SDLLDQM LDQM SDUUDQM SDULDQM A11 to A0 D15 to D0 UDQM LDQM Figure 3.16.8 Connection with SDRAM (1 M word × 16 bits × 2) TMP92CH21 SDCLK SDCKE...
Page 393 TMP92CH21 3.16.3 Limitations arising when using SDRAM Take care to note the following points when using SDRAMC. WAIT access When using SDRAM, some limitation is added when accessing memory other than SDRAM. In WAIT-pin input setting of the Memory Controller, if the setting time is inserted as an external WAIT, set a time less than the Auto-Refresh cycle ×...
Page 394 TMP92CH21 Note when changing access mode If changing access mode from “full page read” to “1 word read”, execute the following program. This program must not be executed on the SDRAM. ; Interrupt Disable (Added) a,(optional external memory ; Dummy read instruction (Added) address) (sdacr1),00001101b ;...
Page 395 TMP92CH21 “Auto Exit” problem when exiting from SDRAM Self-Refresh Mode The SDRAM specification may not be satisfied when using the Self-Refresh function together with CPU stand-by function or changing clock,. because when the CPU releases HALT mode, the Self-Refresh Auto Exit function automatically operates. The following figure shows an example of how to avoid this problem using S/W.
Page 396 TMP92CH21 ; ******** Sample program ********* LOOP1: A, (SDCMM) ; Check the command register clear ANDB A, 00000111B NZ, LOOP1 (SDRCR), 0000010100000010B ; AR stop → SR-ENTRY (SDRCR), 0000---1B ; AR operation NOP × 10 ; Wait for execution of self-refresh entry 7, (PJ) ;...
Page 397 TMP92CH21 3.17 NAND-Flash Controller 3.17.1 Characteristics The NAND-Flash controller (NDFC) is provided with dedicated pins for connecting with NAND-Flash memory. The NDFC also has an ECC calculation function for error correction. Although the NDFC has two channels (channel 0, channel 1), all pins except for Chip Enable are shared between the two channels.
Page 398 TMP92CH21 3.17.2 Block Diagram NAND-Flash Controller Channel 0 (NDFC0) Internal bus bus I/F ND_CE* Registers ND_ALE Register address ND_CLE ND_RE* NAND-Flash I/F timing NDCLE, Host I/F ND_WE* control NDALE, timing control NDRE ND_RB* NDWE D7 to D0 DATA_OUT [7:0] DATA_IN [7:0] D7 to D0, NDR/ B NAND-Flash Controller Channel 1 (NDFC1)
Page 399 TMP92CH21 3.17.3 Operation Description 3.17.3.1 Accessing NAND-Flash Memory The NDFC accesses data on NAND Flash memory indirectly through its internal registers. It also contains the ECC calculating circuits. Please see 3.17.3.2 for details of the ECC. This section explains the operations for accessing the NAND Flash. Basically, set the command in ND0FMCR and then read or write to ND0FDTR.
Page 400 TMP92CH21 (4) Write 16-byte redundant data ND0FMCR: Set 0x9C for the data mode without ECC calculation. ND0FDTR: Write 16-byte redundant data. D520: LPR [23:16] D521: LPR [31:24] D522: CPR [11:6], 2’b11 D525: LPR [7:0] D526: LPR [15:8] D527: CPR [5:0], 2’b11 (5) Run page program ND0FMCR: Set 0x9D for NDCLE signal enable and command mode.
Page 401 TMP92CH21 Read The read sequence is as follows. (1) ND0FMCR: Set 0x7C for ECC data reset. (2) Read 512 bytes ND0FMCR: Set 0x1D for NDCLE signal enable and command mode. ND0FDTR: Set 0x00 for the read command. ND0FMCR: Set 0x1E for NDALE signal enable and address mode. ND0FDTR: Set A [7:0], A [16:9], and A [24:17].
Page 402 TMP92CH21 ID read The ID read sequence is as follows. (1) ND0FMCR: Set 0x1D for NDCLE signal enable and command mode. (2) ND0FDTR: Set 0x90 for the ID Read command. (3) ND0FMCR: Set 0x1E for NDALE signal enable and the address mode. (4) ND0FDTR: Set 0x00.
Page 403 TMP92CH21 3.17.4 Registers Table 3.17.1 NAND-Flash Control Registers for Channel 0 Address Register Register Name 1D00H (1D00H to 1EFFH) ND0FDTR NAND-Flash data transfer register 1CB0H (1CB0H to 1CB5H) ND0ECCRD NAND-Flash ECC-code read register 1CC4H ND0FMCR NAND-Flash mode control register 1CC8H ND0FSR NAND-Flash status register 1CCCH...
Page 404 TMP92CH21 3.17.4.1 NAND-Flash Data Transfer Register (ND0FDTR and ND1FDTR) DATA : Type − : Default Bit (s) Mnemonic Field Name Description DATA DATA NAND-Flash data. Read: Read the data that was read from the NAND-Flash. Write: Write data to the NAND-Flash. Note 1: This register has a 512-address window from 1D00H to 1EFFH since a NAND-Flash page size is either 256 or 512 bytes.
Page 405 TMP92CH21 3.17.4.2 NAND-Flash ECC-code Read Register (ND0ECCRD and ND1ECCRD) ECC-code : Type − : Default Bit (s) Mnemonic Field Name Description ECC-code ECC-code Read calculated ECC data. Note 1: Both ND0ECCRD and ND1ECCRD are assigned to the same address. The NDCR<CHSEL> register determines which channel is accessed.
Page 406 TMP92CH21 3.17.4.3 NAND-Flash Mode Control Register (ND0FMCR and ND1FMCR) ECC1 ECC0 PCNT1 PCNT0 ALE : Type : Default Bits Mnemonic Field Name Description Write enable Write enable (Default: 0) This bit enables the data write operation. When writing the data to the NAND-Flash, set this bit to “1”.
Page 407 TMP92CH21 3.17.4.4 NAND-Flash Status Register (ND0FSR and ND1FSR) BUSY : Type − : Default Bits Mnemonic Field Name Description BUSY BUSY BUSY (Default: Undefined) This bit shows the status of the NAND-Flash. 0: Ready 1: Busy − − Reserved Note: A noise-filter for some states is built into the NDFC, so when the NDR/ B pin changes, a <BUSY> flag is not renewed at the same time.
Page 408 TMP92CH21 3.17.4.5 NAND-Flash Interrupt Status Register (ND0FISR and ND1FISR) : Type : Default Bits Mnemonic Field Name Description − − Reserved Ready Ready (Default: 0) When NDR/ B signal changes from low (BUSY) to High ( READY) and NDFIMR<MRDY> is “1”, this bit is set to “1”. By writing “1”, this bit is cleared to 0.
Page 409 TMP92CH21 3.17.4.7 NAND-Flash Strobe Pulse Width Register (ND0FSPR and ND1FSPR) : Type 0000 : Default Bits Mnemonic Field Name Description − − Reserved Strobe pulse Strobe pulse width (Default: 0000) width These bits set the Low pulse width of the signals.
Page 410 TMP92CH21 3.17.4.8 NAND-Flash Reset Register (ND0FRSTR and ND1FRSTR) : Type : Default Bits Mnemonic Field Name Description − − Reserved Reset Reset (Default: 0) By setting this bit, reset the NDFC (except NDCR<CHSEL> register). By reset, this bit is automatically cleared to “0”. 0: Don’t care 1: Reset Note: After writing <RST>...
Page 411 TMP92CH21 3.17.5 Timing Diagrams 3.17.5.1 Command and Address Cycle ND0FMCR<ALE> = 0 ND0FMCR<CLE> = 0 ND0FMCR<ALE> = 1 ND0FMCR<CLE> = 1 ND0FMCR<CE> = 1 Figure 3.17.10 Command and Address Cycle 2009-06-19 92CH21-409...
Page 412 TMP92CH21 3.17.5.2 Data Read Cycle Figure 3.17.11 shows a timing chart example for a Data Read cycle from the NAND-Flash at ND0FSPR = 02H. Figure 3.17.11 Data Read Cycle Example (ND0FSPR = 02H) 2009-06-19 92CH21-410...
Page 413 TMP92CH21 3.17.5.3 Data Write Cycle Figure 3.17.12 shows a timing chart example for a Data Write cycle to the NAND-Flash at ND0FSPR = 02H. Figure 3.17.12 Data Write Cycle (ND0FSPR = 02H) 2009-06-19 92CH21-411...
Page 414 TMP92CH21 3.17.6 Example of NAND-Flash Use TMP92CH21 100 kΩ NAND-Flash 0 NAND-Flash 1 NDCLE NDALE NDRE NDWE 2 kΩ NDR/ B R/B (Open drain) R/B (Open drain) D [7:0] I/O [7:0] I/O [7:0] External circuits for write protect Note 1: By reset, both pins become input ports (Port 71 and Port 72) And so require pull-up NDRE NDWE...
Page 415 TMP92CH21 3.18 16-Bit Timer/Event Counters (TMRB0) The TMP92CH21 incorporates one multifunctional 16-bit timer/event counter (TMRB0) which has the following operation modes: • 16-bit interval timer mode • 16-bit event counter mode • 16-bit programmable pulse generation (PPG) mode The timer/event counter consists of a 16-bit up counter, two 16-bit timer registers (one of them with a double buffer structure), a 16-bit capture register, two comparators, a capture input controller, a timer flip-flop and a control circuit.
Page 416 TMP92CH21 3.18.1 Block Diagrams Figure 3.18.1 Block Diagram of TMRB0 2009-06-19 92CH21-414...
Page 417 TMP92CH21 3.18.2 Operation of Each Block (1) Prescaler The 5-bit prescaler generates the source clock for timer 0. The prescaler clock (φT0) is a divided clock (divided by 8) from the f This prescaler can be started or stopped using TB0RUN<TB0PRUN>. Counting starts when <TB0PRUN>...
Page 418 TMP92CH21 (3) Timer registers (TB0RG0H/L and TB0RG1H/L) These 16-bit registers are used to set the interval time. When the value in the up counter UC10 matches the value set in this timer register, the comparator match detect signal will go active. Setting data for both Upper and Lower timer registers is always needed.
Page 419 TMP92CH21 (4) Capture registers (TB0CP0H/L and TB0CP1H/L) These 16-bit registers are used to latch the values in the up counters. All 16 bits of data in the capture registers should be read. For example, using a 2-byte data load instruction or two 1-byte data load instructions. The least significant byte is read first, followed by the most significant byte.
Page 420 TMP92CH21 3.18.3 SFRs TMRB0 Run Register − TB0RUN Bit symbol TB0RDE I2TB0 TB0PRUN TB0RUN (1180H) Read/Write Reset State Function Double Always IDLE2 TMRB0 Up counter write “0” UC10 buffer 0: Stop Prescaler 0: Disable 1: Operate 0: Stop and clear 1: Enable 1: Run (Count up) Count operation...
Page 421 TMP92CH21 TMRB0 Mode Register − − TB0MOD Bit symbol TB0CP0I TB0CPM1 TB0CPM0 TB0CLE TB0CLK1 TB0CLK0 (1182H) Read/Write Reset State Read-modify Function Always write “0” Execute Capture timing Control TMRB0 source clock -write software up counter 00: Disable 00: Reserved instruction is capture 01: φT1 0: Disable...
Page 422 TMP92CH21 TMRB0 Flip-Flop Control Register − − TB0FFCR Bit symbol TB0C1T1 TB0C0T1 TB0E1T1 TB0E0T1 TB0FF0C1 TB0FF0C0 (1183H) Read/Write Reset State Function Always write “11”. TB0FF0 inversion trigger Control TB0FF0 Read-modify 0: Disable trigger 00: Invert -write 1: Enable trigger 01: Set instruction is 10: Clear Invert when...
Page 423 TMP92CH21 TMRB0 register － TB0RG0L bit Symbol (1188H) Read/Write Reset State Undefined － TB0RG0H bit Symbol (1189H) Read/Write Reset State Undefined － TB0RG1L bit Symbol (118AH) Read/Write Reset State Undefined － TB0RG1H bit Symbol (118BH) Read/Write Reset State Undefined － TB0CP0L bit Symbol (118CH)
Page 424 TMP92CH21 3.18.4 Operation in Each Mode (1) 16-bit interval timer mode Generating interrupts at fixed intervals. In this example, the interrupt INTTB01 is set to be generated at fixed intervals. The interval time is set in the timer register TB0RG1H/L. ←...
Page 425 TMP92CH21 The following block diagram illustrates this mode. TB0RUN<TB0RUN> TB0OUT0 (PPG output) Selector φT1 φT4 16-bit up counter φT16 Clear (TB0FF0) UC10 Match 16-bit comparator 16-bit comparator Selector TB0RG0H/L TB0RG0H/L- Register buffer 10 TB0RG1H/L TB0RUN<TB0RDE> Internal data bus Figure 3.18.8 Block Diagram of 16-Bit Mode The following example shows how to set 16-bit PPG output mode: ←...
Page 426 TMP92CH21 3.19 Touch Screen Interface (TSI) The TMP92CH21 has an interface for a 4-terminal resistor network touch screen. This interface supports two procedures: an X/Y position measurement and touch detection. Each procedure is executed by setting the TSI control register (TSICR0 and TSICR1) and using an internal AD converter.
Page 427 TMP92CH21 3.19.2 Touch Screen Interface (TSI) Control Register TSI Control Register TSICR0 Bit symbol TSI7 PTST TWIEN PYEN PXEN MYEN MXEN (01F0H) Read/Write Reset State Function 0: Disable Detection INT4 interrupt 1: Enable condition 0 : OFF 0 : OFF 0 : OFF 0 : OFF control...
Page 428 TMP92CH21 3.19.3 Touch Detection Procedure The Touch detection procedure shows procedure until a pen is touched by the screen and it is detected. By touching, TSI generates interrupt (INT4) and this procedure terminates. After an X/Y position measuring procedure is terminated, return to this procedure and wait for the next touch.
Page 429 TMP92CH21 Reset counter for debounce time Start counter for debounce time Debounce Debounce Debounce time time time INT4 After pen is released, INT4 can be issued again. INT4 is generated by matching counter and specified debounce time. IINT4 is not generated by matching counter and specified debounce period because it is an edge-type interrupt.
Page 430 TMP92CH21 3.19.4 X/Y Position Measuring Procedure During the INT4 routine, execute an X/Y position measuring procedure as below. <X position measurement> Make both the SPX and SMX switches ON, and the SPY and SMY switches OFF. With this setting, an analog voltage which shows the X position will be input to the PG3/MY/AN3 pin.
Page 431 TMP92CH21 3.19.5 Flow Chart for TSI (1) Touch detection procedure (2) X/Y position measurement procedure Main routine: INT4 routine: TSICR0 ← 98H TSICR1 ← XXH (Voluntary) <X position measurement> ･TSICR0 ← 85H Execute main routine ･AD conversion for AN3 ･Store the result <Y position measurement>...
Page 432 TMP92CH21 3.20 I S (Inter-IC Sound) An I S format compatible serial output circuit is built-in. This product can be used in digital audio system applications by connecting LSI for sound generation (e.g., a DA converter). This circuit has both I S mode and general SIO mode.
Page 433 TMP92CH21 3.20.1 Block Diagram Prescaler 2 4 8 I2SCKO I2SCKO control <MCK1:0> <TXE, CLKE> ÷ 4 I2SWS I2SWS control TA1OUT <I2SWCK> <FMT, I2SWLVL> <BUSY> 16-byte FIFO (Right) 16 bits <DIR> (2 bytes × 8) Data selector, Write pointer FIFO control interrupt Read pointer control...
Page 434 TMP92CH21 3.20.2 The following tables show the SFR for I S. This I S is connected to the CPU by the 16-bit data bus. When the CPU accesses the SFR, use a 2-byte load instruction. I2SCTL0 Register I2SCTL0 Bit symbol BUSY MCK1 MCK0...
Page 435 TMP92CH21 3.20.3 Explanation of I S Mode (1) Connection example Figure 3.20.3 shows an example with external LSI. TMP92CH21 (Transmitter) (Receiver) P92/I2SWS P90/I2SCKO P91/I2SDO DATA Example: DA converter Note: After reset, P90 to P92 are placed in a high-impedance state. Connect each pin with a pull-up or pull-down resistor as necessary.
Page 436 TMP92CH21 Write to FIFO <TXE> I2SWS pin I2SCKO pin I2SDO pin <BUSY> INTI2S Figure 3.20.4 Whole Timing Diagram I2SWS pin 10 MHz I2SCKO pin I2SDO pin LSB MSB Bit7 Bit6 Bit0 Bit7 Bit6 Bit0 Bit7 Figure 3.20.5 Detail Timing Diagram (3) Notes INTI2S timing INTI2S is generated after the last data of FIFO is loaded to the internal shifter.
Page 437 TMP92CH21 3.20.4 Explanation of SIO Mode (1) Connection example Figure 3.20.6 shows an example with external LSI. TMP92CH21 (Transmitter) (Receiver) P90/I2SCKO P91/I2SDO Port Example: Shift register Note: Since P90 to P91 become high impedance by reset, connect a pull-up or pull-down resistor if necessary. Figure 3.20.6 Example with External LSI (2) Procedure A 32-byte FIFO is built-in.
Page 438 TMP92CH21 Write to FIFO <TXE> I2SCKO pin I2SDO pin <BUSY> INTI2S Figure 3.20.7 Whole Timing 10 MHz I2SCKO pin I2SDO pin Bit0 Bit1 Bit7 Bit0 Bit1 Bit7 Figure 3.20.8 Detail Timing (3) Notes INTI2S timing INTI2S is generated after the last data of FIFO is loaded to the internal shifter. FIFO is now empty and it is possible to write the next data.
Page 439 TMP92CH21 3.21 Boot ROM A boot ROM is built-in to download user’s boot program. Three downloading methods are supported. 3.21.1 Operation Mode There are 2 operation modes: MULTI mode and BOOT mode. Each mode is set according to the status of the AM1 and AM0 pins when is asserted.
Page 440 TMP92CH21 3.21.2 Hardware Specification for Internal Boot ROM (1) Memory map Figure 3.21.1 shows a memory map of BOOT mode. An 8-Kbyte ROM is built-in and it is mapped to address 3FE000H to 3FFFFFH. In MULTI mode, the boot ROM is not mapped and its area is mapped as an external area.
Page 441 TMP92CH21 3.21.3 Outline of Boot Operation There are 3 downloading methods: NAND flash, UART and USB. After reset, a boot program in the boot ROM operates as shown in the Figure 3.21.2 flow chart. Internal RAM use is the same regardless of downloading method, and is shown in Figure 3.21.3.
Page 442 TMP92CH21 002000H Work area for boot program (4 Kbytes) 003000H Download area for user program (10 Kbytes) 005800H Stack area for boot program (2 Kbytes) Figure 3.21.3 Internal RAM Use 2009-06-19 92CH21-440...
Page 443 TMP92CH21 (1) Port setting The boot program port settings are shown in Table 3.21.3, and Table 3.21.4 shows PCB design. These port settings must be carefully noted when designing an application system. The remaining ports are not set, so they maintain their status after reset. Table 3.21.3 Port Setting Port Setting by Boot Program Port...
Page 444 TMP92CH21 Table 3.21.4 How to Design PCB Boot Method Port Function UART NAND flash Not affected by UART boot. Not affected by USB boot. NAND Output Connect to NAND flash and NDRE If the NAND flash is not used in flash pull-up by 100 kΩ...
Page 445 TMP92CH21 (2) I/O registers setting by boot program Table 3.21.5 shows I/O register setting by boot program. Take particular note of these set values when using an application system program which continues to run without asserting a reset after a boot sequence is executed . Also take note of the status of the CPU registers and internal RAM following execution of a boot sequence.
Page 446 TMP92CH21 3.21.4 Download from NAND flash (1) Connection example Figure 3.21.4 shows an example of NAND flash. (A 16-bit SDRAM is used as program memory). 100 kΩ 2 kΩ 100 kΩ P84, PJ6, NDCLE PJ5, NDALE P71, NDRE TMP92CH21 P72, NDWE P75, NDR/ B PF7, SDCLK...
Page 447 TMP92CH21 (3) Data format The download data consists of the boot identification code (4 bytes), user program size (2 bytes) and user program (max 10 Kbytes). These should be assigned (programmed) to NAND flash as shown in Figure 3.21.5. Also program the ECC code in the redundant area of the NAND flash, the block status area and thedata status area .
Page 448 TMP92CH21 User program (max 10 Kbytes) This refers to a user program that is loaded to internal RAM. When creating a user program, note the following points. • Set start address to 3000H Beforehand, program (write) the user program to NAND flash in binary format.
Page 449 TMP92CH21 (4) Error check item The items checked by the boot program are given below. If an error occurs in any check, the boot program will cancel downloading from NAND flash and skip to the next operation (recognizing UART or USB). Supported NAND flash The boot program reads a device code from NAND flash and checks whether it is supported or not.
Page 450 TMP92CH21 For reference, details of calculation flow are given below. Make XOR data by calculating exclusive OR after both ECC code from NDFC and NAND flash are placed to 4-byte data as below. Lower 2 bytes: Line parity Upper 2 bytes: Column parity (Valid data of column parity is lower 6-bit in upper 2 bytes) If XOR data equals “0”, it will terminate normally because the ECC code is the...
Page 451 TMP92CH21 3.21.5 Download with UART (1) Connection example Figure 3.21.8 shows an example of UART. (A 16-bit NOR flash is used as program memory.) UART 3 pins TXD1, PF0 (output) Level RXD1, PF1 (input) P82, shifter P70, PJ2, SRWR TMP92CH21 NOR flash D0 to D15 D0 to D15...
Page 452 TMP92CH21 (3) UART data transfer format Table 3.21.7 to Table 3.21.12 show the supported frequency, data transfer format, baud rate modification commands, operation commands, version management information, and frequency measurement result with data storing location, respectively. Please also refer to the description of boot program operation in the following pages. Table 3.21.7 Supported Frequency (f OSCH 6.00...
Page 453 TMP92CH21 Table 3.21.9 Baud Rate Modification Command Baud Rate (bps) 9600 19200 38400 57600 115200 Modification Command Note 1:If f is either 16.0, 20.0, 20.58 or 25.0 MHz, 115200 bps is not supported. OSCH Note 2: If f is 10.0 MHz, both 57600 and 115200 bps are not supported. OSCH Note 3: If f is 6.00, 8.00 or 9.00 MHz, then 38400, 57600 and 115200 bps are not...
Page 454 TMP92CH21 The seventh byte is used to send information of the measured frequency. The PC should check that the frequency of the resonator is measured correctly. The receive data in the eighth byte is the baud rate modification data. The five kinds of baud rate modification data shown in Table 3.21.9 are available.
Page 455 TMP92CH21 Error code The boot program sends the processing status to the PC using various codes. The error codes are listed in the table below. Table 3.21.13 Error Codes Error Code Meaning of Error Code Baud rate modification error occurred. Operation command error occurred.
Page 456 TMP92CH21 d) Notes on Intel Hex format (Binary) After receiving the checksum of a record, the device waits for the start mark (3AH for “ : ”) of the next record. Therefore, the device ignores all data received between records during that time unless the data is 3AH. Make sure that once the PC program has finished sending the checksum of the end record, it does not send anything and waits for 2 bytes of data to be received (upper and lower bytes of SUM).
Page 457 TMP92CH21 Error when receiving user program If the following errors occur in Intel Hex format when receiving the user program, the device goes to an idle state. When the record type is not 00H, 01H, and 02H When a checksum error occurs Error between frequency measurement and baud rate The boot program measures the resonator frequency when receiving matching data.
Page 458 TMP92CH21 (5) Further notes Handshake function The TMP92CH21 has a pin, but boot programs do not use it. RS-232C connector When the boot program is running, do not connect or disconnect an RS-232C connector. Software on PC Special application software is needed on the PC. 2009-06-19 92CH21-456...
Page 459 TMP92CH21 3.21.6 Download with USB (1) Connection example Figure 3.21.9 shows an example of USB. (16-bit NOR flash is used as program memory.) PUCTL PC6, KO8, LDIV R4 = P82, 100 kΩ R1 = 1.5 kΩ P70, R2 = 27 Ω PJ2, SRWR D−...
Page 460 TMP92CH21 An outline flowchart is given below. (Legend) Control type Bulk type Host (PC) TMP92CH21 Transmit GET_DESCRIPTOR Recognition for connection Transmit DESCRIPTOR information Transmit MICON information command Preparing MICON Transmit MICON information data information data Confirming data Transmitting data Transmit MICON information command Converting Intel Hex format Preparing MICON...
Page 461 TMP92CH21 The vendor request command table is shown below. Table 3.21.16 Vendor Request Command Table Value of Command Name Outline Notes Request MICON (Microcomputer) This is transmitted after a setup Transmit information command stage is terminated by bulk in microcomputer transfer type.
Page 462 TMP92CH21 The standard request command table is shown below. Table 3.21.18 The Standard Request Command Table Standard Request Response Medthod By hardware, GET_STATUS automatically CLEAR_FEATURE SET_FEATURE SET_ADDRESS GET_DISCRIPTOR Not supported SET_DISCRIPTOR By hardware, GET_CONFIGRATION automatically SET_CONFIGRATION GET_INTERFACE SET_INTERFACE Ignored SYNCH_FRAME The information transmitted by GET_DISCRIPTOR is shown below.
Page 463 TMP92CH21 Configuration Descriptor Field Name Value Meaning bLength 9 bytes Configuration descriptor bDescriptorType Total length (32 bytes) in which each descriptor wTotalLength 0020H of configuration descriptor, interface and endpoint is added. Interface is 1 bNumInterfaces Configuration number 1 bConfigurationValue Index value of string descriptor in which this iConfiguration configuration name is shown (Not used).
Page 464 TMP92CH21 The information transmitted by the MICON information command is shown below. Table 3.21.20 Information Transmitted by MICON Information Command Micon Information ASCII Code “TMP92CH21FG” 54H, 4DH, 50H, 39H, 32H, 43H, 48H, 32H, 31H, 46H, 47H, 20H, 20H, 20H, 20H The information transmitted by the result information command is shown below.
Page 465 TMP92CH21 (3) Description of USB boot program operation The boot program provides the following RAM loader function. The data, which is transmitted by the PC in Intel Hex format, is loaded to the internal RAM. After loading normally, the user program will begin to execute. The first received address is set as the starting address.
Page 466 TMP92CH21 Notes on user program format (Binary) After receiving the checksum of a record, the device waits for the start mark (3AH for “: ”) of the next record.The device therefore ignores all data received between records during that time unless the data is 3AH. The first record type is not needed as an address record because the initial value of the address pointer is 00H.
Page 467 TMP92CH21 (4) Further notes USB connector When the boot program is running, do not connect or disconnect the USB connector. Software on PC Special USB device driver and application software is needed on the PC. 2009-06-19 92CH21-465...
Page 468 TMP92CH21 Electrical Characteristics Absolute Maximum Ratings Parameter Symbol Rating Unit −0.5 to 4.0 Power Supply Voltage −0.5 to VCC + 0.5 Input Voltage Output Current Output Current (MX, MY pin) −2 Output Current −15 Output Current (PX, PY pin) Σ I Output Current (Total) Σ...
Page 469 TMP92CH21 DC Electrical Characteristics (1/2) = 3.3 ± 0.3V/X1 = 6 to 40 MHz/Ta = −20 to 70°C = 2.7 − 3.6V/X1 = 6 to 27 MHz/Ta = −20 to 70°C Parameter Symbol Typ. Unit Condition X1 = 6 to 40 MHz Power supply voltage XT1 = 30 to 34 kHz (DVCC = AVCC)
Page 470 TMP92CH21 DC Electrical Characteristics (2/2) Parameter Symbol Typ. Unit Condition = 1.6 mA Output low voltage 0.45 = −400 μA Output high voltage 0.9 × V = −20 μA Internal resistor (ON) = 0.2V IMon MX, MY pins Ω = 3.0 to 3.6 V Internal resistor (ON) −0.2V IMon...
Page 471 TMP92CH21 AC Characteristics 4.3.1 Basic Bus Cycle Read cycle Variable Parameter Symbol 40 MHz 36 MHz 27 MHz Unit 1 OSC period (X1/X2) 166.7 27.7 37.0 2 System clock period ( = T) 333.3 55.5 74.0 0.5 T − 15 3 SDCLK low width 12.7 0.5 T −...
Page 472 TMP92CH21 (1) Read cycle (0 waits) SDCLK WAIT A0~A23 D0~D31 Data input SRxxB SRWR Note: The phase relation between X1 input signal and the other signals is undefined. The above timing chart is an example. 2009-06-19 92CH21-470...
Page 473 TMP92CH21 (2) Write cycle (0 waits) SDCLK WAIT A0~A23 WRxx D0~D31 Data output SRxxB SRWR Note: The phase relation between X1 input signal and the other signals is undefined. The above timing chart is an example. 2009-06-19 92CH21-471...
Page 474 TMP92CH21 (3) Read cycle (1 wait) SDCLK WAIT A0 to A23 D0 to D31 Data input (4) Write cycle (1 wait) SDCLK WAIT A0 to A23 WRxx D0 to D31 Data output 2009-06-19 92CH21-472...
Page 475 TMP92CH21 Page ROM Read Cycle 4.3.2 (1) 3-2-2-2 mode Variable Parameter Symbol 40 MHz 36 MHz 27 MHz Unit 1 System clock period ( = T) 166.7 55.5 2 A0, A1 → D0 to D31 input 2.0T − 50 3 A2 to A23 → D0 to D31 input 3.0T −...
Page 476 TMP92CH21 SDRAM Controller AC Characteristics 4.3.3 Variable Parameter Symbol 40 MHz 36 MHz 27 MHz Unit 1 Ref/active to ref/active command period 2 Active to precharge command period 12210 3 Active to read/write command delay 55.5 time 4 Precharge to active command period 55.5 5 Active to active command period 166.5...
Page 477 TMP92CH21 (1) SDRAM read timing (CPU access or LCDC normal access) SDCLK SDxxDQM SDCS SDRAS SDCAS SDWE 16-bit data bus A1 to A10 Column Column A12 to A15 Column D0 to D15 Data input 32-bit data bus A1 to A11 Column Column A13 to A15...
Page 478 TMP92CH21 (2) SDRAM write timing (CPU access) SDCLK SDxxDQM SDCS SDRAS SDCAS SDWE 16-bit data bus A1 to A12 Column Column A12 to A15 Column D0 to D15 Data output 32-bit data bus A1 to A11 Column Column A13 to A15 Column D0 to D31 Data output...
Page 479 TMP92CH21 (3) SDRAM burst read timing (Start of burst cycle) SDCLK SDxxDQM SDCS SDRAS SDCAS SDWE A1 to A11 or Column A1 to A10 A12 or A11 Column A13 to A15 or A12 to A15 D0 to D31 Data input Data input Data input 2009-06-19...
Page 480 TMP92CH21 (4) SDRAM burst read timing (End of burst cycle) SDCLK SDxxDQM SDCS SDRAS SDCAS SDWE A1 to A11 or Column Column A1 to A10 A12 or A11 Column Column A13 to A15 or Column A12 to A15 D0 to D31 Data input Data input Data input...
Page 481 TMP92CH21 (5) SDRAM initialize timing SDCLK SDxxDQM SDCS SDRAS SDCAS SDWE A1 to A12 A20 to A23 (BS0 and BS1) 2009-06-19 92CH21-479...
Page 482 TMP92CH21 (6) SDRAM refresh timing SDCLK SDxxDQM SDCS SDRAS SDCAS SDWE (7) SDRAM self refresh timing SDCLK SDCKE SDxxDQM SDCS SDRAS SDCAS SDWE 2009-06-19 92CH21-480...
Page 483 TMP92CH21 NAND Flash Controller AC Characteristics 4.3.4 Variable Parameter Symbol 40 MHz 36 MHz 27 MHz Unit (1 + n) T − 12 low width 43.5 NDRE (1 + n) T − 25 − data access time 30.5 NDRE REA (3.0 V) (1 + n) T −...
Page 484 TMP92CH21 Serial Channel Timing 4.3.5 (1) SCLK input mode (I/O interface mode) Variable Parameter Symbol 40 MHz 36 MHz 27 MHz Unit μs SCLK cycle 0.888 1.184 Output data → SCLK rising/falling /2 − 4T − 110 SCLK rising/falling → Output data hold /2 + 2T + 0 SCLK rising/falling →...
Page 485 TMP92CH21 4.3.7 LCD Controller (SR mode) Variable Parameter Symbol 40 MHz 36 MHz 27 MHz Unit LCP0 clock period ( = tm) 0.5 tm − 12 LCP0 high width 43.5 0.5 tm − 12 LCP0 low width 43.5 Data valid → LCP0 falling 0.5 tm −...
Page 486 TMP92CH21 S Timing (I S, SIO Mode) 4.3.8 Variable Parameter Symbol 40 MHz 36 MHz 27 MHz Unit I2SCKO clock period − 15 I2SCKO high width 0.5 t − 15 I2SCKO low width 0.5 t − 15 I2SDO, I2SWS setup time 0.5 t −...
Page 487 TMP92CH21 AD Conversion Characteristics Parameter Symbol Typ. Unit − 0.2 Analog reference voltage (+) REFH + 0.2 Analog reference voltage (−) REFL AD converter power supply voltage AD converter ground Analog input voltage REFL REFH Analog current for analog reference voltage 1.35 <VREFON>...
Page 488 TMP92CH21 Recommended Oscillation Circuit The TMP92CH21 has been evaluated by the oscillator vender below. Use this information when selecting external parts. Note: The total load value of the oscillator is the sum of external loads (C1 and C2) and the floating load of the actual assembled board.
Page 489 TMP92CH21 Table of Special function registers (SFRs) The SFRs include the I/O ports and peripheral control registers allocated to the 4-Kbyte address space from 000000H to 001FFFH. (1) I/O Port (11) UART/serial channel (2) Interrupt control (12) USB controller (3) Memory controller (13) AD converter (4) MMU (14) Watchdog timer...
Page 490 TMP92CH21 Table 5.1 I/O Register Address Map [1] Port Address Name Address Name Address Name Address Name 0000H 0010H P4 0020H P8 0030H PC 1H P8FC2 2H PCCR 3H P4FC 3H P8FC 3H PCFC 4H P1 4H P5 4H P9 5H P9FC2 6H P1CR 6H P9CR...
Page 491 TMP92CH21 [2] INTC Address Name Address Name Address Name Address Name 00D0H INTE12 00E0H Reserved 00F0H INTE0AD 0100H DMA0V 1H INTE34 1H Reserved 1H INTETC01 1H DMA1V 2H Reserved 2H INTETC23 2H DMA2V 3H INTEUSB 3H INTETC45 3H DMA3V 4H INTETA01 4H Reserved 4H INTETC67 4H DMA4V...
Page 492 TMP92CH21 [5] CGEAR, PLL [6] LCDC1 Address Name Address Name Address Name 10E0H SYSCR0 0280H LCDMODE0 0290H 1H SYSCR1 1H LCDMODE1 1H LCDRP10 2H SYSCR2 2H LCDFFP 2H LCDRP32 3H EMCCR0 3H LCDDVM 3H LCDRP54 4H EMCCR1 4H LCDSIZE 4H LCDRP76 5H EMCCR2 5H LCDCTL0 5H LCDGP10...
Page 493 TMP92CH21 [7] TSI [8] SDRAMC [9] 8-bit timer [10] 16-bit timer Address Name Address Name Address Name Address Name 01F0H TSICR0 0250H SDACR1 1100H TA01RUN 1180H TB0RUN 1H TSICR1 1H SDACR2 2H SDRCR 2H TA0REG 2H TB0MOD 3H SDCMM 3H TA1REG 3H TB0FFCR 4H TA01MOD 5H TA01FFCR...
Page 494 TMP92CH21 [12] USB controller (1/2) Address Name Address Name Address Name Address Name 0500H Descriptor- 0780H ENDPOINT0 0790H EP0_STATUS 07A0H 1H ENDPOINT1 1H EP1_STATUS 1H EP1_SIZE_L_B 067FH (384 bytes) 2H ENDPOINT2 2H EP2_STATUS 2H EP2_SIZE_L_B 3H ENDPOINT3 3H EP3_STATUS 3H EP3_SIZE_L_B 8H EP0_SIZE_L_A 9H EP1_MODE 9H EP1_SIZE_L_A...
Page 495 TMP92CH21 [12] USB controller (2/2) Address Name Address Name 07E0H Port_Status 07F0H USBINTFR1 1H FRAME_L 1H USBINTFR2 2H FRAME_H 2H USBINTFR3 3H ADDRESS 3H USBINTFR4 4H USBINTMR1 5H USBINTMR2 6H USBREADY 6H USBINTMR3 7H USBINTMR4 8H Set Descriptor STALL 8H USBCR1 Note: Do not access un-named addresses.
Page 496 TMP92CH21 [13] 10-bit ADC [14] WDT Address Name Address Name Address Name 12A0H ADREG0L 12B0H 1300H WDMOD 1H ADREG0H 1H WDCR 2H ADREG1L 3H ADREG1H 4H ADREG2L 5H ADREG2H 6H ADREG3L 7H ADREG3H 8H Reserved 8H ADMOD0 9H Reserved 9H ADMOD1 AH Reserved AH ADMOD2 BH Reserved...
Page 497 TMP92CH21 [17] NAND flash controller Address Name Address Name Address Name Address Name 1CC0H 1CD0H ND0FIMR 1CE0H 1CF0H ND1FIMR 4H ND0FMCR 4H ND0FSPR 4H ND1FMCR 4H ND1FSPR 8H ND0FSR 8H ND0FRSTR 8H ND1FSR 8H ND1FRSTR CH ND0FISR CH ND1FISR Address Name Address Name...
Page 498 TMP92CH21 [18] I Address Name 0800H I2SBUFR 8H I2SBUFL EH I2SCTL0 Note: Do not access un-named addresses. 2009-06-19 92CH21-496...
Page 499 TMP92CH21 (1) I/O ports (1/7) Symbol Name Address Port 1 0004H Data from external port (Output latch register is cleared to “0”) Port 2 0008H Data from external port (Output latch register is cleared to “0”) Port 3 000CH Data from external port (Output latch register is cleared to “0”) Port 4 0010H Port 5...
Page 500 TMP92CH21 (1) I/O ports (2/7) Symbol Name Address P17C P16C P15C P14C P13C P12C P11C P10C Port 1 0006H P1CR control (Prohibit register RMW) 0: Input 1: Output Port 1 0007H P1FC function (Prohibit 0:Port register RMW) 1:Data bus (D8 to D15) P27C P26C P25C...
Page 501 TMP92CH21 (1) I/O ports (3/7) Symbol Name Address P76C P75C P72C P71C 0: Input 0: Input 0: Input port, 0: Input port Port 7 001EH port, port, 1: Output 1: Output P7CR control (Prohibit NDR/ port, port, WAIT register RMW) NDWE @ 1: Output 1: Output...
Page 502 TMP92CH21 (1) I/O ports (4/7) Symbol Name Address PA6C PA5C PA4C PA3C Port A 002AH control (Prohibit PACR register RMW) 0: Input port or key-in 1: LD11 to LD8 output PA7F PA6F PA5F PA4F PA3F PA2F PA1F PA0F Port A 002BH function (Prohibit...
Page 503 TMP92CH21 (1) I/O ports (5/7) Symbol Name Address PJ6C PJ5C 004EH Port J PJCR control (Prohibit register RMW) 0:Input 1: Output PJ7F PJ6F PJ5F PJ4F PJ3F PJ2F PJ1F PJ0F 004FH Port J PJFC function (Prohibit register RMW) 0: Port 0: Port 0: Port 0: Port 0: Port...
Page 504 TMP92CH21 (1) I/O ports (6/7) Symbol Name Address P17D P16D P15D P14D P13D P12D P11D P10D Port 1 P1DR drive 0081H register Input/Output buffer drive register for standby mode P27D P26D P25D P24D P23D P22D P21D P20D Port 2 P2DR drive 0082H register...
Page 505 TMP92CH21 (1) I/O ports (7/7) Symbol Name Address PF7D PF4D PF3D PF2D PF1D PF0D Port F Input/Outp drive PFDR 008FH ut buffer register drive Input/Output buffer drive register for standby mode register for standby mode PG3D PG2D Port G PGDR drive 0090H register...
Page 506 TMP92CH21 (2) Interrupt control (1/4) Symbol Name Address INT2 INT1 INT1 & INT2 I2M2 I2M1 I2M0 I1M2 I1M1 I1M0 INTE12 00D0H enable INT4 INT3 INT3 & INT4 I4M2 I4M1 I4M0 I3M2 I3M1 I3M0 INTE34 00D1H enable INTTA1 (TMRA1) INTTA0 (TMRA0) INTTA0 &...
Page 507 TMP92CH21 (2) Interrupt control (2/4) Symbol Name Address − INTALM4 − − − − INTALM4 IA4C IA4M2 IA4M1 IA4M0 INTEALM4 00E7H enable Always write “0” − INTRTC − − − − INTRTC IRM2 IRM1 IRM0 INTERTC 00E8H enable Always write “0” −...
Page 508 TMP92CH21 (2) Interrupt control (3/4) Symbol Name Address INTAD INT0 INT0 & IADC IADM2 IADM1 IADM0 I0M2 I0M1 I0M0 INTE0AD INTAD 00F0H enable INTTC1 (DMA1) INTTC0 (DMA0) INTTC0 & ITC1C ITC1M2 ITC1M1 ITC1M0 ITC0C ITC0M2 ITC0M1 ITC0M0 INTETC01 INTTC1 00F1H enable INTTC3 (DMA3) INTTC2 (DMA2)
Page 509 TMP92CH21 (2) Interrupt control (4/4) Symbol Name Address DMA0V5 DMA0V4 DMA0V3 DMA0V2 DMA0V1 DMA0V0 DMA0 DMA0V 0100H start vector DMA0 start vector DMA1V5 DMA1V4 DMA1V3 DMA1V2 DMA1V1 DMA1V0 DMA1 DMA1V 0101H start vector DMA1 start vector DMA2V5 DMA2V4 DMA2V3 DMA2V2 DMA2V1 DMA2V0 DMA2...
Page 510 TMP92CH21 (3) Memory controller (1/3) Symbol Name Address B0WW2 B0WW1 B0WW0 B0WR2 B0WR1 B0WR0 BLOCK0 0140H Write waits Read waits CS/WAIT B0CSL (Prohibit 001: 0 waits 010: 1 wait 001: 0 waits 010: 1 wait control RMW) 101: 2 waits 110: 3 waits 101: 2 waits 110: 3 waits...
Page 511 TMP92CH21 (3) Memory controller (2/3) Symbol Name Address B3WW2 B3WW1 B3WW0 B3WR2 B3WR1 B3WR0 BLOCK3 014CH Write waits Read waits CS/WAIT B3CSL (Prohibit 001: 0 waits 010: 1 wait 001: 0 waits 010: 1 wait control RMW) 101: 2 waits 110: 3 waits 101: 2 waits 110: 3 waits...
Page 512 TMP92CH21 (3) Memory controller (3/3) Symbol Name Address Memory M0V20 M0V19 M0V18 M0V17 M0V16 M0V15 M0V14-9 M0V8 address MAMR0 0142H mask register 0 0: Compare enable 1: Compare disable M0S23 M0S22 M0S21 M0S20 M0S19 M0S18 M0S17 M0S16 Memory start MSAR0 0143H address register 0...
Page 513 TMP92CH21 (4) MMU (1/2) Symbol Name Address LOCALX LOCALPX register for 01D0H Bank for Specify the bank number for the LOCAL-X area program LOCAL-X (Since bank 0 is overlapping with the COMMON area, 0: Disable this filed must not be specified as 0.) 1: Enable LOCALY LOCALPY...
Page 514 TMP92CH21 (4) MMU (2/2) Symbol Name Address LOCALZ LOCALRZ register for 01DBH Bank for Specify the bank number for the LOCAL-Z area read LOCAL-Z (Since bank 3 is overlapping with the COMMON area, 0: Disable this filed must not be specified as 3.) 1: Enable LOCALX LOCALWX...
Page 515 TMP92CH21 (5) Clock gear, PLL Symbol Name Address XTEN WUEF System SYSCR0 clock control 10E0H H-OSC L-OSC Warm-up register 0 (fc) (fs) timer 0: Stop 0: Stop 1: Oscillation 1: Oscillation SYSCK GEAR2 GEAR1 GEAR0 System Select Select gear value of high SYSCR1 clock control 10E1H...
Page 516 TMP92CH21 (6) LCD controller (1/6) Symbol Name Address RAMTYPE1 RAMTYPE0 SCPW1 SCPW0 MODE3 MODE2 MODE1 MODE0 Display RAM LD bus transmission Mode setting speed 0000: Built-in RAM type 0101: STN 8bpp (256) mode 0 0280H LCDMODE0 00: Internal SRAM 00: Reserved 0001: SR 1bpp (mono) 0110: STN 12bpp (4096) register...
Page 517 TMP92CH21 (6) LCD controller (2/6) Symbol Name Address SCC7 SCC6 SCC5 SCC4 SCC3 SCC2 SCC1 SCC0 source LCDSCC 0287H clock counter LCDC source clock counter bit7 to bit0 register PCPV2 PCPV1 PCPV0 clock LCDCCR0 0288H Pre LCP1 CLK: LCP1 pulse counter number register 0...
Page 518 TMP92CH21 (6) LCD controller (3/6) Symbol Name Address green LCDGP10 0295H palette 256 color STN mode 256 color STN mode register 10 GREEN1 level setting GREEN0 level setting green LCDGP32 0296H palette 256 color STN mode 256 color STN mode register 32 GREEN3 level setting GREEN2 level setting...
Page 519 TMP92CH21 (6) LCD controller (4/6) Symbol Name Address Start address LSARAL 02A0H register A area (L) Start address for A area (bit7 to bit0) SA15 SA14 SA13 SA12 SA11 SA10 Start address LSARAM 02A1H register A area (M) Start address for A area (bit15 to bit8) SA23 SA22 SA21...
Page 520 TMP92CH21 (6) LCD controller (5/6) Symbol Name Address OE007 OE006 OE005 OE004 OE003 OE002 OE001 OE000 LCDOE00 OE0 control 02B0H register 0 OE0 control gate driver of TFT panel OE017 OE016 OE015 OE014 OE013 OE012 OE011 OE010 LCDOE01 OE0 control 02B1H register 1 OE0 control gate driver of TFT panel...
Page 521 TMP92CH21 (6) LCD controller (6/6) Symbol Name Address OE207 OE206 OE205 OE204 OE203 OE202 OE201 OE200 LCDOE20 OE2 control 02D0H register 0 OE2 control gate driver of TFT panel OE217 OE216 OE215 OE214 OE213 OE212 OE211 OE210 LCDOE21 OE2 control 02D1H register 1 OE2 control gate driver of TFT panel...
Page 522 TMP92CH21 (7) Touch screen I/F Symbol Name Address TSI7 PTST TWIEN PYEN PXEN MYEN MXEN Touch 0: Disable screen I/F Detection INT4 TSICR0 01F0H 1: Enable control interrupt condition 0 : OFF 0 : OFF 0 : OFF 0 : OFF register 0 control 0: no...
Page 523 TMP92CH21 (9) 8-bit timer Symbol Name Address TA0RDE I2TA01 TA01PRUN TA1RUN TA0RUN TMRA01 Double IDLE2 TA01RUN 1100H TMRA01 UP counter UP counter buffer 0: Stop register (UC0) prescaler (UC1) 0: Disable 1: Operate 0: Stop and clear 1: Enable 1: Run (Count up) −...
Page 524 TMP92CH21 (10) 16-bit timer Symbol Name Address − TB0RDE I2TB0 TB0PRUN TB0RUN TMRB0 Double Always IDLE2 TB0RUN 1180H TMRB0 UP counter buffer write “0” 0: Stop register (UC10) prescaler 0: Disable 1: Operate 0: Stop and clear 1: Enable 1: Run (Count up) −...
Page 525 TMP92CH21 (11) UART/serial channel (1/2) Symbol Name Address Serial 1200H channel 0 SC0BUF (Prohibit buffer R (Receiving)/W (Transmission) RMW) register Undefined EVEN OERR PERR FERR SCLKS R (Clear 0 after reading) Serial Undefined channel 0 0: SCLK0 ↑ Receive Parity Parity 1: Error 0: Baud...
Page 526 TMP92CH21 (11) UART/Serial channel (2/2) Symbol Name Address Serial 1208H channel 1 SC1BUF (Prohibit buffer R (Receiving) /W (Transmission) RMW) register Undefined EVEN OERR PERR FERR SCLKS R (Clear 0 after reading) Serial Undefined 0: SCLK1 ↑ channel 1 Receive Parity Parity 1: Error...
Page 527 TMP92CH21 (12) USB controller (1/6) Symbol Name Address Descriptor RAM 0 0500H Descriptor RAM0 register Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Descriptor RAM 1 0501H Descriptor RAM1 register Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Descriptor RAM 2 0502H Descriptor RAM2 register...
Page 528 TMP92CH21 (12) USB controller (2/6) Symbol Name Address TOGGLE SUSPEND STATUS[2] STATUS[1] STATUS[0] FIFO_DISABLE STAGE_ERR Endpoint 0 status 0790H EP0_STATUS register TOGGLE SUSPEND STATUS[2] STATUS[1] STATUS[0] FIFO_DISABLE STAGE_ERR Endpoint 1 status 0791H EP1_STATUS register TOGGLE SUSPEND STATUS[2] STATUS[1] STATUS[0] FIFO_DISABLE STAGE_ERR Endpoint 2 status 0792H...
Page 529 TMP92CH21 (12) USB controller (3/6) Symbol Name Address Endpoint 1 DATASIZE9 DATASIZE8 DATASIZE7 size 07B1H EP1_SIZE_H_B register High B Endpoint 2 DATASIZE9 DATASIZE8 DATASIZE7 size 07B2H EP2_SIZE_H_B register High B Endpoint 0 DATASIZE9 DATASIZE8 DATASIZE7 size 07B3H EP3_SIZE_H_B register High B DIRECTION REQ_TYPE1 REQ_TYPE0...
Page 530 TMP92CH21 (12) USB controller (4/6) Symbol Name Address SetupRece 07C8H SetupReceived ived register REMOTEWAKEUP ALTERNATE[1] ALTERNATE[0] INTERFACE[1] INTERFACE[0] CONFIG[1] CONFIG[0] Current_ 07C9H Current_Config Config register S_INTERFACE G_INTERFACE S_CONFIG G_CONFIG G_DESCRIPT S_FEATURE C_FEATURE G_STATUS Standard- Request 07CAH Standard Request register SOFT_RESET G_PORT_STS G_DEVICE_ID VENDOR CLASS ExSTANDARD...
Page 531 TMP92CH21 (12) USB controller (5/6) Symbol Name Address Reserved7 Reserved6 PaperError Select NotError Reserved2 Reserved1 Reserved0 Port status 07E0H Port Status register − T[6] T[5] T[4] T[3] T[2] T[1] T[0] Frame register 07E1H FRAME_L T[10] T[9] T[8] T[7] CREATE FRAME_STS1 FRAME_STS0 Frame 07E2H FRAME_H...
Page 532 TMP92CH21 (12) USB controller (6/6) Symbol Name Address MSK_URST_STR MSK_URST_END MSK_SUS MSK_RESUME MSK_CLKSTOP MSK_CLKON interrupt 07F4H USBINTMR1 mask When read 0: Be not masked When write 0: Clear flag register 1 1: − 1: Be masked EP1_MSK_FA EP1_MSK_EA EP1_MSK_FB EP1_MSK_EB EP2_MSK_FA EP2_MSK_EA EP2_MSK_FB...
Page 533 TMP92CH21 (13) AD converter (1/2) Symbol Name Address − − EOCF ADBF ITM0 REPEAT SCAN Always Always Repeat Scan mode 0: Every AD mode write “0” write “0” mode conversion conversion 0: Fixed conversion 1 time ADMOD0 control 12B8H 0: Single end flag channel start...
Page 534 TMP92CH21 (14) Watchdog timer Symbol Name Address − − WDTE WDTP1 WDTP0 I2WDT RESCR Select detecting time Always IDLE2 Always 1: Internally WDMOD mode 1300H control 00: 2 write “0” write “0” 0: Stop connects register 1: Enable 01: 2 1: Operate WDT out 10: 2...
Page 535 TMP92CH21 (15) RTC (Real time clock) Symbol Name Address Second SECR 1320H register Undefined “0” is read 40 sec. 20 sec. 10 sec. 8 sec. 4 sec. 2 sec. 1 sec. Minute MINR 1321H register Undefined “0” is read 40 min. 20 min.
Page 536 TMP92CH21 (16) Melody/alarm generator Symbol Name Address Alarm pattern 1330H register Alarm pattern set − − − − ALMINV MELALM Melody/ Free run counter Alarm Output alarm MELALMC 1331H control frequency frequency control 00: Hold invert 0: Alarm register Always write “0” 01: Restart 1: Invert 1: Melody...
Page 537 TMP92CH21 (17) NAND flash controller (1/2) Symbol Name Address NAND flash data ND0FDTR 1D00H transfer Undefined register Data window to read/write NAND flash ECC1 ECC0 PCNT1 PCNT0 Chip Power Control Address Command 0: Disable ECC circuit NAND enable Latch Latch write 11 (at <CE>=X): Reset flash mode...
Page 538 TMP92CH21 (17) NAND flash controller (2/2) Symbol Name Address NAND flash data ND1FDTR 1D00H transfer Undefined register Data window to read/write NAND flash ECC1 ECC0 PCNT1 PCNT0 Chip Power Control Address Command 0: Disable ECC circuit NAND enable Latch Latch write 11 (at <CE>=X): Reset flash...
Page 539 TMP92CH21 (18) I Symbol Name Address R15/R7 R14/R6 R13/R5 R12/R4 R11/R3 R10/R2 R9/R1 R8/R0 0800H S FIFO I2SBUFR (Prohibit buffer (R) Undefined RMW) Register for transmitting buffer (FIFO) (Right channel) L15/L7 L14/L6 L13/L5 L12/L4 L11/L3 L10/L2 L9/L1 L8/L0 0808H S FIFO I2SBUFL (Prohibit buffer (L)
Page 540 TMP92CH21 Points of Note and Restrictions Notation (1) The notation for built-in I/O registers is as follows: Register symbol <Bit symbol> Example: TA01RUN<TA0RUN> denotes bit TA0RUN of register TA01RUN. (2) Read-modify-write instructions (RMW) An instruction in which the CPU reads data from memory and writes the data to the same memory location in one instruction.
Page 541 TMP92CH21 Notes (1) AM0 and AM1 pins These pins are connected to the V (Power supply level) or the V (Grand level) pin. Do not alter the level when the pin is active. (2) Reserved address areas The 16 bytes area (FFFFF0H ∼ FFFFFFH) cannot be used since it is reserved for use as internal area.
Page 542 TMP92CH21 Package Dimensions Package Name: LQFP144-P-1616-0.40C Unit: mm Note: Palladium plating 2009-06-19 92CH21-540...
Page 543 • The information contained herein is presented only as guidance for Product use. No responsibility is assumed by TOSHIBA for any infringement of patents or any other intellectual property rights of third parties that may result from the use of Product. No license to any intellectual property right is granted by this document, whether express or implied, by estoppel or otherwise.
Page 544 TMP92CH21 2009-06-19 92CH21-542...

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