Toshiba TLCS-900/H1 Series Data Book page 22

3.3.2 SFR
SYSCR0
bit Symbol XEN
(10E0H)
Read/Write
After reset
High-frequen
cy oscillator
(fc)
0: Stop
1: Oscillation
Function
SYSCR1
bit Symbol
(10E1H)
Read/Write
After reset
Function
SYSCR2
bit Symbol
(10E2H)
Read/Write R/W
After reset
Write '0' .
Function
Note1: The unassigned register,SYSCR0<bit5 to 3>,SYSCR0<bit1 to 0>,SYSCR1<bit 7 to 4>,
and SYSCR2<bit6,bit1 to 0> are read as undefined-value.
Note2: By reset, low-frequency oscillator is enabled.
7 6 5
XTEN
R/W
1 1
Low-frequen
cy oscillator
(fs)
0: Stop
1: Oscillation
7 6 5
7 6 5
WUPTM1
R/W
0 1
Warm-Up Timer
00: reserved
8
01: 2 /inputted frequency
14
10:2
16
11:2
Figure 3.3.3 SFR for system clock
92CH21 - 18
4 3 2
WUEF
R/W
Warm-up
Timer
0: Write
Don't care
1: Write
start timer
0: Read
end warm-up
1: Read
do not end
warm-up
4 3 2
SYSCK GEAR2
R/W
0
Select Select gear value of high frequency (fc)
system 000: fc
clock. 001: fc/2
0:fc 010: fc/4
1:fs 011: fc/8
100: fc/16
101: (reserved)
110: (reserved)
111: (reserved)
4 3 2
WUPTM0 HALTM1 HALTM0
R/W R/W R/W
0 1
HALT mode
00: reserved
01: STOP mode
10: IDLE1 mode
11: IDLE2 mode
TMP92CH21
1 0
0
1 0
GEAR1 GEAR0
R/W
1 0 0
1 0
1