Toshiba TLCS-900/H1 Series Data Book page 255
32bit micro controller
Hide thumbs
Also See for TLCS-900/H1 Series:
Table of Contents
Advertisement
When you write data to FIFO in sending, you confirm condition of two packets, and you must load
after you consider order of loading packetA, B. When you set loading data number, set to which A，
Bpacket, you judge by showing PACKET_ACTIVEbit. This packet of Bit0 is loading packet now.
You must caution that logic of PACKET_ACTIVEbit in receiving and sending is reverse.
Below is this sequence.
Interrupt by EPx_EMPTY_A(B)
DATASET register・check
DATASET = 0
DATASET = 1
Wait sending
r
rest data
・ WR number of payload×2
If sending finish normally,
It clear applicable bit of DATASET
Wait sending event
DATASET register
・Check bit of EPx_DSET_A
・Check bit of EPx_DSET_B
Sending number ＞ payload×2
in applicable endpoint
・Total = Total −payload×2
If reach to payload DATASET,
set 1 to applicable bit of register.
Wait INToken
Figure 3.10.13 Sending sequencein dual packet mode
92CH21-251
IDLE
Sending event
Sendind data
distinction
Sending number＜ payload×2
・ WR
number
number
・Total = 0
EOP register
・WR 0 to only bit of
applicable endpoint.
Wait sending
Completion of sending
TMP92CH21
of
sending
・Must access to EOP register in sending short
packet.
・Contorol-transfer-type is only single mode.
Advertisement
Table of Contents
