Toshiba TLCS-900/H1 Series Data Book page 336

Internal system clock
(fSYS)
A23 to A0
/RD
D32 to D0 or D15 to D0
8bit bus
LCP
LD7 to LD0
LCP
LD7 to LD0
LCP
LD7 to LD0
4bit bus
LCP
LD3 to LD0
LCP
LD3 to LD0
4/8bit bus
LCP
LD7 to LD0
* When using internal SRAM, it always select 32bit bus width and 0-wait, 1CLK access.
Under Development
N N+1 N+2
IN IN+1 IN+2
OUT OUT OUT+1 OUT+1
OUT
OUT OUT OUT+1 OUT+1 OUT+2 OUT+2 OUT+3 OUT+3 OUT+4 OUT+4
OUT
Fastest timing diagram for external SRAM, 0-WAIT
OUT OUT OUT+1 OUT+1 OUT+2 OUT+2 OUT+3 OUT+3 OUT+4 OUT+4
Timing diagram for internal SRAM
92CH21-332
N+3 N+4 N+5
IN+4 IN+5
IN+3
OUT+2 OUT+2 OUT+3 OUT+3 OUT+4 OUT+4
OUT+1 OUT+2 OUT+3
OUT
OUT+1 OUT+2 OUT+ ３
TMP92CH21
32bit bus width, monochrome
/4Gray/256 color
16bit bus width, monochrome
/4Gray/256 color
32bit bus width, 16Gray
16bit bus, 16Gray
32bit bus, monochrome
/4/16Gra/256 color
16bit bus, monochrome
4/16Gray/256 color
Monochrome/4/16Gray
/256 color