Toshiba TLCS-900/H1 Series Data Book page 326

32bit micro controller
Hide thumbs Also See for TLCS-900/H1 Series:
Table of Contents

Advertisement

Relation of Memory map image and Output data
Monochrome (1 bpp (bit per pixel))
Display memory image
Address 0
LSB
D0
0
1
2 3
4 5
6
LD bus output sequence
4bitA type
LD0
0 to 4 to 8 to 12 ~
LD1
1 to 5 to 9 to 13 ~
LD2
2 to 6 to 10 to 14 ~
LD3
3 to 7 to 11 to 15 ~
LD4
not use
LD5
not use
LD6
not use
LD7
not use
  4Gray (2 bpp)
Display memory image
Address 0
LSB
D0
0
1
2 3
4 5
6
1pixel
LD bus output sequence
4bitA type
LD0
1-0 to 9- 8 to 17-16 ~
LD1
3-2 to 11-10 to 19-18 ~
LD2
5-4 to 13-12 to 21-20 ~
LD3
7-6 to 15-14 to 23-22 ~
LD4
not use
LD5
not use
LD6
not use
LD7
not use
Under Development
Address 1
7
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
4bitB type
LD0
LD1
LD2
LD3
LD4
LD5
LD6
LD7
Address 1
7
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
4bitB type
LD0
LD1
LD2
LD3
LD4
LD5
LD6
LD7
Relation of Memory map image and Output data (1)
92CH21-322
Address 2
4 to 0 to 12 to 8 ~
5 to 1 to 13 to 9 ~
6 to 2 to 14 to 10 ~
7 to 3 to 15 to 11 ~
not use
not use
not use
not use
Address 2
9- 8 to 1-0 to 25-24~
11-10 to 3-2 to 27-26 ~
13-12 to 5-4 to 29-28 ~
15-14 to 7-6 to 31-30 ~
not use
not use
not use
not use
    TMP92CH21
Address 3
    MSB
       
D31
8bit
LD0
0 to 8 ~
LD1
1 to 9 ~
LD2
2 to 10 ~
LD3
3 to 11 ~
LD4
4 to 12 ~
LD5
5 to 13 ~
LD6
6 to 14 ~
LD7
7 to 15 ~
Address 3
    MSB
       
D31
8bit
LD0
1 - 0 to 17-16 ~
LD1
3 - 2 to 19-18 ~
LD2
5 - 4 to 21-20 ~
LD3
7- 6 to 23-22 ~
LD4
9- 8 to 25-24 ~
LD5
11-10 to 27-26 ~
LD6
13-12 to 29-28 ~
LD7
15-14 to 31-30 ~

Advertisement

Table of Contents
loading

This manual is also suitable for:

Tmp92ch21fg

Table of Contents