Toshiba TLCS-900/H1 Series Data Book page 46

Although the control registers used for setting the transfer source and transfer destination
addresses are 32 bits wide, this type of register can only output 24-bit addresses. Accordingly,
micro DMA can only access 16 Mbytes (the upper eight bits of a 32-bit address are not valid).
Three micro DMA transfer modes are supported: one-byte transfers, two-byte (one-word)
transfer and four-byte transfer. After a transfer in any mode, the transfer source and transfer
destination addresses will either be incremented or decremented, or will remain unchanged.
This simplifies the transfer of data from I/O to memory, from memory to I/O, and from I/O to I/O.
For details of the various transfer modes, see Section 3.4.2 (1), Detailed description of the
Transfer Mode Register.
Since a transfer counter is a 16-bit counter, up to 65536 micro DMA processing operations
can be performed per interrupt source (provided that the transfer counter for the source is
initially set to 0000H).
Micro DMA processing can be initiated by any one of 34 different interrupts – the 33
interrupts shown in the micro DMA start vectors in Table 3.4.1 and a micro DMA soft start.
Figure 3.4.2 shows a 2-byte transfer carried out using a micro DMA cycle in Transfer Destination
Address INC Mode (micro DMA transfers are the same in every mode except Counter Mode).
(The conditions for this cycle are as follows: external 8-bit bus, 0 waits, and even-numbered
transfer source and transfer destination addresses).
A0∼23
Figure 3.4.2 Timing for micro DMA cycle
:
State (1),(2) Instruction fetch cycle (prefetches the next instruction code)
:
State (3) Micro DMA read cycle
:
State (4) Micro DMA write cycle
State (5) : (The same as in state (1), (2) )
1 state
(1) (2) (3)
f
SYS
src
92CH21 - 42
(4) (5)
dst
TMP92CH21