Toshiba TLCS-900/H1 Series Data Book page 135

− 1
6
2
− 1
7
2
− 1
8
2
(5) Settings for each mode
Table 3.7.4 shows the SFR settings for each mode.
Register name
<Bit Symbol>
Function
8-bit timer × 2 channels
16-bit timer mode
8-bit PPG × 1 channel
8-bit PWM × 1 channel
8-bit timer × 1 channel
Note:"−" = Don't care
Table 3.7.3 PWM cycle
φT1
25.2 µs ( 39.7 kHz )
50.8 µs ( 19.6 kHz )
102 µs ( 9.80 kHz )
Table 3.7.4 Timer mode setting registers
<TA01M1:0> <PWM01:00>
Timer mode PWM cycle
−
00
−
01
−
10
− 1, 2 − 1, 2
6 7
2
11
(01, 10, 11)
−
11
92CH21 - 131
PWM Interval (at fsys = 20MHz)
φT4
100.8 µs ( 9.92 kHz )
203.2 µs ( 4.92 kHz )
408 µs ( 2.45 kHz )
TA01MOD
<TA1CLK1:0>
Upper timer
input clock
Lower timer match,
External clock,
φT1, φT16, φT256
(00, 01, 10, 11)
External clock,
−
External clock,
−
External clock,
− 1
8
−
φT1, φT16 , φT256
(01, 10, 11)
TMP92CH21
φT16
403.2 µs ( 2.48 kHz )
810 µs ( 1.23 kHz )
1.63 ms ( 0.61 kHz )
TA1FFCR
<TA0CLK1:0> <TAFF1IS>
Lower timer Timer F/F
input clock invert signal select
0: Lower timer output
φT1, φT4, φT16
1: Upper timer output
(00, 01, 10, 11)
φT1, φT4, φT16
(00, 01, 10, 11)
φT1, φT4, φT16
(00, 01, 10, 11)
φT1, φT4, φT16
(00, 01, 10, 11)
−
Output disabled
−
−
−