Toshiba TLCS-900/H1 Series Data Book page 45

3.4.2 Micro DMA processing
In addition to general-purpose interrupt processing, the TMP92CH21 also includes a micro
DMA function. Micro DMA processing for interrupt requests set by micro DMA is performed at
the highest priority level for maskable interrupts (level 6), regardless of the priority level of the
interrupt source.
Because the micro DMA function has been implemented with the cooperative operation of CPU,
when CPU is a state of stand-by by HALT instruction, the requirement of micro DMA will be
ignored (pending).
Micro DMA is suppoted 8 channels and can be transferred continuously by specifying the
micro DMA burst function in the following.
(1)Micro DMA operation
When an interrupt request is generated by an interrupt source specified by the Micro DMA
Start Vector Register, the micro DMA triggers a micro DMA request to the CPU at interrupt
priority level 6 and starts processing the request. The eight micro DMA channels allow micro
DMA processing to be set for up to eight types of interrupt at once.
When micro DMA is accepted, the interrupt request flip-flop assigned to that channel is
cleared. Data in one-byte or two-byte or four-byte blocks, is automatically transferred at once
from the transfer source address to the transfer destination address set in the control register,
and the transfer counter is decremented by 1. If the value of the counter after it has been
decremented is not 0, DMA processing ends with no change in the value of the micro DMA start
vector register. If the value of the decremented counter is 0, a Micro DMA Transfer End interrupt
(INTTC0 to INTTC7) is sent from the CPU to the interrupt controller. In addition, the micro DMA
start vector register is cleared to 0, the next micro DMA operation is disabled and micro DMA
processing terminates.
If micro DMA requests are set simultaneously for more than one channel, priority is not
based on the interrupt priority level but on the channel number: the lower the channel number,
the higher the priority (Channel 0 thus has the highest priority and Channel 7 the lowest).
If an interrupt request is triggered for the interrupt source in use during the interval between
the time at which the micro DMA start vector is cleared and the next setting, general-purpose
interrupt processing is performed at the interrupt level set. Therefore, if the interrupt is only
being used to initiate micro DMA (and not as a general-purpose interrupt), the interrupt level
should first be set to 0 (i.e. interrupt requests should be disabled).
If micro DMA and general-purpose interrupts are being used together as described above,
the level of the interrupt which is being used to initiate micro DMA processing should first be set
to a lower value than all the other interrupt levels. In this case, edge-triggered interrupts are the
only kinds of general interrupts which can be accepted.
92CH21 - 41
TMP92CH21