Toshiba TLCS-900/H1 Series Data Book page 352

32bit micro controller

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Sequential access type

Data transmission to LCD driver is executed by move instruction of CPU.

After setting mode of operation to control register, when move instruction of CPU is executed

LCDC outputs chip select signal to LCD driver connected to the outside from control pin (LCP0

etc.). Therefore control of data transmission numbers corresponding to LCD size is controlled by

instruction of CPU. There are 2 kinds of address of LCD driver in this case, and which is chosen

determines by LCDCTL <MMULCD> register.

It corresponds to LCD driver which has every 1 byte of instruction register and display data

address at this time into either of 1FE0H-1FE7H. (SEQUENTIAL ACCESS TYPE)

LCDC0L/LCDC0H/LCDC1L/LCDC1H/LCDC2L/LCDC2H/LCDR0L/LCDR0H register

System clock : f

Note1. This waveform is the case of 3-state access.

Example of access timing for RAM built-in type LCD driver (Wait=0)

Under Development

Depend on External LCDD specification

[Write Cycle]

WAIT sampling

Note the different rising timing for D1BSCP etc.

[Read Cycle]