Toshiba TLCS-900/H1 Series Data Book page 149

3.9.1 Block diagrams
prescaler
φT0
2 4
φT2
Serial clock generation circuit
BR0CR
<BR0CK1, 0>
φ
T0
φ
T2
φ
T8
φ
T32
f
IO
SCLK0
I/O Interface Mode
SCLK0
Receive
Counter
(UART only ÷ 16)
RXDCLK
SC0MOD0 Receive
<RXE>
Receive Buffer1 (shift register)
RXD0
RB8 Receive Buffer2 (SC0BUF)
8 16 32 64
φT8 φT32
BR0CR BR0ADD
<BR0S3 to <BR0K3 to 0>
BR0CR
<BR0ADDE>
Baud rate
generator
÷2
SC0MOD0
<WU>
Control
SC0CR
<PE>
Parity control
Error flag
SC0CR
<OERR><PERR><FERR>
Internal bus
Figure 3.9.2 Block diagram of the Serial Channel 0
92CH21 - 145
TA0TRG
(from TMRA0)
UART
Mode
SC0MOD0 SC0MOD0
<SC1, SC0> <SM1, SM0>
I/O
interface mode
SC0CR
<IOC>
Serial channel
interrupt
control
TXDCLK
<EVEN>
TB8 Transmission Buffer (SC0BUF)
SIOCLK
Transmision
counter
(UART only ÷ 16)
Transmission
Control
SC0MOD0
<CTSE>
TMP92CH21
INT request
INTRX0
INTTX0
/CTS0
TXD0