Toshiba TLCS-900/H1 Series Data Book page 383
32bit micro controller
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3.17.4.7 NAND Flash Strobe Pulse Width Register (ND0FSPR, ND1FSPR)
Bit
Mnemonic
7 : 4
3 : 0
SPW
Strobe Pulse
Width
Figure 3.17.4(7) NAND Flash Strobe Pulse Width Register (ND0FSPR ,ND1FSPR)
Field Name
Reserved
Strobe Pulse Width (Default: 0000)
These bits specify the Low pulse width of the /NDRE and /NDWE signals.
The low pulse width is the value of this field plus one f
92CH21-379
7
6
5
4
Description
TMP92CH21
3
2
1
0
SPW
R/W
: Type
0000
: Default
clock.
SYS
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