Operational Description; Cpu Core Functions; Memory Address Map; Program Memory (Otp) - Toshiba TLCS-870/C Series Manual

2. Operational Description

2.1 CPU Core Functions

The CPU core consists of a CPU, a system clock controller, and an interrupt controller.
This section provides a description of the CPU core, the program memory, the data memory, and the reset circuit.

2.1.1 Memory Address Map

The TMP86PM29BUG memory is composed OTP, RAM, DBR(Data buffer register) and SFR(Special func-
tion register). They are all mapped in 64-Kbyte address space. Figure 2-1 shows the
address map.
SFR
RAM
DBR
OTP

2.1.2 Program Memory (OTP)

The TMP86PM29BUG has a 32768 bytes (Address 8000H to FFFFH) of program memory (OTP ).

2.1.3 Data Memory (RAM)

The TMP86PM29BUG has 1536bytes (Address 0040H to 063FH) of internal RAM. The first 192 bytes
(0040H to 00FFH) of the internal RAM are located in the direct area; instructions with shorten operations are
available against such an area.
0000
H
64 bytes
003F
H
0040
H
1536
bytes
063F
H
0F80
H
128
bytes
0FFF
H
8000
H
32768
bytes
FFC0
H
Vector table for vector call instructions
(32 bytes)
FFDF
H
FFE0
H
Vector table for interrupts
(32 bytes)
FFFF
H
Figure 2-1 Memory Address Map
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Special function register includes:
SFR:
I/O ports
Peripheral control registers
Peripheral status registers
System control registers
Program status word
Random access memory includes:
RAM:
Data memory
Stack
DBR: Data buffer register includes:
Peripheral control registers
Peripheral status registers
LCD display memory
OTP:
Program memory
TMP86PM29BUG
TMP86PM29BUG
memory