Toshiba TLCS-900/H1 Series Data Book page 113

3.6.6 Cautions
(1) Note the timing between /CS and /RD
If the parasitic capacitance of
Signal), it is possible that an uninttended read cycle occurs due to a delay in the read signal. Such
an unintended read cycle may cause a trouble as in the case of (a) in Figure 3.6(1).
SDCLK
(20MHz)
A23 to 0
/CSm
/CSn
/RD
Example: When using an externally connected
commands, note that the toggle bit may not be read out correctly. If the Read signal in
the cycle immediately preceding the access to the
time, as shown in Figure 3.6(2), an unitended read cycle like the one shown in (b) may
occur.
SDCLK
(20MHz)
A23 to 0
NOR-Flash
Chip select
/RD
Toggle bit
When the toggle bit reverse with this unexpected read cycle, CPU always reads same value of
the toggle bit, and cannot read the toggle bit correctly. To avoid this
function control is recommended.
the /RD(read signal )
Figure 3.6(1) Read Signal Delay Read cycle
Memory
Toggle bit RD
access
(b)
Figure 3.6(2) NOR-Flash
92CH21-109
is greater than that of the
(a)
NOR-Flash which users JEDEC standard
NOR-Flash
cycle
Toggle Bit Read cycle
phenomenon, the data polling
TMP92CH21
/CS(Chip Select
does not go High in