Toshiba TLCS-900/H1 Series Data Book page 214

32bit micro controller
Hide thumbs Also See for TLCS-900/H1 Series:
Table of Contents

Advertisement

 
3.10.3.28 Set Descriptor STALL register
This register set Set-Descriptor-request whether returns STALL automatically in data stage or
status stage.
  Set Descriptor STALL  
7
symbol
-
R/W
-
    Bit0:S_D_STALL
0:Software contorol  (default)
1:Automatically STALL
3.10.3.29 Descriptor RAM
  This register use for store of Descriptor in RAM.  Size of Descriptor is 384byte.But you must write
to following format to Descriptor RAM-sturucture-sample when store Descriptor.
  Descriptor RAM
(0500H to 067FH)
7
symbol
D7
R/W
R/W
   
  Possible timing in RD/WR is only before detect in USB_RESETand performing SET_DESCRIPTOR
request.
  This SET_DESCRIPTOR-request-transaction-time is until access EOP register since INT_SETUP
assert. If there is rewriting request of Descriptorin in SET_DESCRIPTOR, you process request
belowsequence.
1) Read out every packet Descriptor transfer in SET_DESCRIPTOR request.
2) When finish reading out Descriptor number of last packet, you write all Descriptor RAM to
Descriptor.
3) When finish writing, you execute INIT_DESCRIPTOR of command register.
4) When finish all transaction, access EOP register and finish status stage.
5) When recive into INT_STATUS, it is finished status stage.
  You don't have to execute INIT_DESCRIPTOR command when connect host. It is reading
automatically start detect in USB_RESET.
(07E8H)
6
5
-
-
-
-
6
5
D6
D5
R/W
R/W
92CH21-210
4
3
-
-
-
-
4
3
D4
D3
R/W
R/W
TMP92CH21
2
1
-
-
S_D_STALL
-
-
2
1
D2
D1
R/W
R/W
0
W
0
D0
R/W
 

Advertisement

Table of Contents
loading

This manual is also suitable for:

Tmp92ch21fg

Table of Contents