Toshiba TLCS-900/H1 Series Data Book page 37

Table 3.3.5 Source of Halt state clearance and Halt clearance operation
Status of Received Interrupt
Halt mode
INTWDT
INT0 to 4 (Note1)
INTALM0 to 4
INTTA0 to 3,INTTB00 to 01
INTRX0 to 1,TX0 to 1
INTTBO0,INTI2S
INTAD
INTKEY
INTRTC
INTUSB
INTLCD
RESET
%: After clearing the Halt mode, CPU starts interrupt processing. (RESET initializes the microcont.)
&: After clearing the Halt mode, CPU resumes executing starting from instruction following the HALT
instruction.
×: It can not be used to release the halt mode.
−: The priority level (interrupt request level) of non-maskable interrupts is fixed to 7, the highest priority level.
There is not this combination type.
*1: Releasing the halt mode is executed after passing the warmming-up time.
Note 1: When the Halt mode is cleared by an INT0 interrupt of the level mode in the interrupt enabled status,
hold level H until starting interrupt processing. If level L is set before holding level L, interrupt
processing is correctly started.
(Example - releasing IDLE1 Mode)
An INT0 interrupt clears the Halt state when the device is in IDLE1 Mode.
Address
8203H
8206H
8209H
820BH
820EH
INT0
820FH
Interrupt Enabled
(interrupt level) ≥ (interrupt mask)
IDLE2
%
%
%
%
%
%
%
%
%
%
%
%
LD (IIMC), 00H
LD (INTE0AD), 06H
EI 5
LD (SYSCR2), 28H
HALT
LD XX, XX
92CH21 - 33
IDLE1 STOP
×
×
*1
% %
×
%
× ×
× ×
× ×
× ×
*1
% %
*1
% %
*1
% %
× ×
% %
; Selects INT0 interrupt rising edge.
; Sets INT0 interrupt level to 6.
; Sets interrupt level to 5 for CPU.
; Sets Halt mode to Idle1 Mode.
; Halts CPU.
TMP92CH21
Interrupt Disabled
(interrupt level) < (interrupt mask)
IDLE2 IDLE1
− −
& &
& &
× ×
× ×
× ×
× ×
& &
& &
& &
× ×
% %
INT0 interrupt routine
RETI
STOP
−
*1
&
×
×
×
×
×
*1
&
*1
&
*1
&
×
%