Fig. 3.16.2 (7) Connection with SDRAM(1MWord×16bit×2)
TMP92CH21
SDCLK
SDCKE
A13
A12
A11-A0
D15-D0
D31-D16
SDRAS
SDCAS
SDWE
SDCS
SDLUDQM
SDLLDQM
SDUUDQM
SDULDQM
Fig. 3.16.2 (8) Connection with SDRAM(512KWord×32bit)
TMP92CH21
SDCLK
SDCKE
A10-A0
D31-D0
SDRAS
SDCAS
SDWE
SDCSL
SDUUDQM
SDULDQM
SDLUDQM
SDLLDQM
CLK
CKE
BS1
BS0
A11-A0
D15-D0
RAS
CAS
WE
CS
UDQM
LDQM
CLK
CKE
BS1
BS0
A11-A0
D15-D0
RAS
CAS
WE
CS
UDQM
LDQM
CLK
CKE
A12
BS1
A11
BS0
A10-A0
D31-D0
RAS
CAS
WE
CS
DQM3
DQM2
DQM1
DQM0
512Kword × 4Banks × 32bits
92CH21-366
TMP92CH21