Toshiba TLCS-900/H1 Series Data Book page 160

(12) Timing generation
# In UART Mode
Receiving
Mode
Interrupt timing
Framing error timing
Parity error timing
Overrun error timing
Note: In 9-Bit and 8-Bit + Parity Modes, interrupts coincide with the ninth bit pulse.
Thus, when servicing the interrupt, it is necessary to wait for a 1-bit period (to
allow the stop bit to be transferred) to allow checking for a framing error.
Transmitting
Mode
Interrupt timing
" I/O interface
Transmission SCLK Output Mode
Interrupt
timing
SCLK Input Mode
Receiving SCLK Output Mode
Interrupt
timing
SCLK Input Mode
9-Bit
(Note)
Center of last bit Center of last bit
(bit 8) (parity bit)
Center of stop bit Center of stop bit
Center of last bit
―
(parity bit)
Center of last bit Center of last bit
(bit 8) (parity bit)
9-Bit
Just before stop bit is Just before stop bit is
transmitted transmitted
Immediately after rise of last SCLK signal.
(See figure 3.9 19.)
Immediately after rise of last SCLK signal Rising Mode, or
immediately after fall in Falling Mode. (See figure 3.9 20.)
Timing used to transfer received to data Receive Buffer 2 (SC0BUF)
(i.e. immediately after last SCLK). (See figure 3.9 21.)
Timing used to transfer received data to Receive Buffer 2 (SC0BUF)
(i.e. immediately after last SCLK). (See figure 3.9 22.)
92CH21 - 156
8-Bit + Parity
8-Bit, 7-Bit + Parity, 7-Bit
(Note)
Center of stop bit
Center of stop bit
Center of last bit
(parity bit)
Center of stop bit
8-Bit + Parity 8-Bit, 7-Bit + Parity, 7-Bit
Just before stop bit is transmitted
TMP92CH21