Cpu; Reset - Toshiba TMP91C815F Data Book

3. OPERATION
This following describes block by block the functions and operation of the TMP91C815F.
Notes and restrictions for eatch book are outlined in " 7, Precautions and Restrictions at the end of this manual.

3.1 CPU

The TMP91C815 incorporates a high-performance 16-bit CPU (the 900/L1-CPU). For CPU operation, see
the "TLCS-900/L1 CPU".
The following describe the unique function of the CPU used in the TMP91C815; these functions are not
covered in the TLCS-900/L1 CPU section.
3.1.1

Reset

When resetting the TMP91C815 microcontroller, ensure that the power supply voltage is within the
operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the
RESET input to Low level at least for 10 system clocks (ten states: 80 µs at 4 MHz).
After Reset, Clock doubler circuit is set to x1 mode, and also Clock gear is set to x1/16 mode. It means
that the initial clock mode starts x1/64 speed mode against the maximum speed of TMP91C815.
When the reset is accept, the CPU:
• Sets as follows the program counter (PC) in accordance with the reset vector stored at address
FFFF00H to FFFF02H:
PC<0 to 7>
PC<15 to 8> ← value at FFFF01H address
PC<23 to 16> ←value at FFFF02H address
• Sets the stack pointer (XSP) to 100H.
• Sets bits <IFF2:0> of the status register(SR) to 111 (sets the interrupt level mask register to level
7).
• Sets the <MAX> bit of the status register(SR) to 1 (MAX mode).
(Note: As this product does not support MIN mode, do not write a 0 to the <MAX> )
• Clears bits <RFP2:0> of the status register(SR) to 000 (sets the register bank to 0 ).
When reset is released,the CPU starts executing instructions in accordance with the program counter
settings. CPU internal registers not mentioned above do not change when the reset is released.
When the reset is accepted, the CPU sets internal I/O, ports, and other pins as follows.
• Initializes the internal I/O registers.
• Sets the port pins, including the pins that also act as internal I/O, to general-purpose input or
output port mode.
(Note1) The CPU internal register(except to PC,SR,XSP) and internal RAM data do not change by
resetting.
Figure 3.1.1 is a reset timing chart of the TMP91C815.
← value at FFFF00H address
91C815-9
TMP91C815