Toshiba TLCS-900/H1 Series Data Book page 323

3.14.3 Shift-register type LCD driver control mode (SR mode, STN color)
3.14.3.1 Description of operation
Set the mode of operation, start address of source data save memory, gray-scale level and LCD
size to control registers before setting start register.
After set start register LCDC outputs bus release request to CPU and read data from source
memory. After finish data read from source data, LCDC cancels the bus release request and CPU
will re-start. After that LCDC transmits data of volume of LCD size to external LCD driver through
LD bus (Special data bus for only LCDD). At this time, control signals (LCP0 etc.) connected LCD
driver output specified waveform synchronizes with data transmission.
SR mode LCDC, during data read from source memory (during DMA operation), CPU is stopped
by internal BUSREQ signal.
LCD controller generates some control signals (LFR, LBCD, LLP etc) from base clock: LCDSCC.
LCDSCC is base clock for LCD controller, made from system clock: f
TMP92CH21 has special clock generator for LCDC. Detail refresh rate of LCD frame can set
from this special generator. This generator made by 8-bit counter and 1/16 speed clock of system
clock.
NOTE1) SR mode LCDC, during data read from source memory (during DMA operation),
CPU is stopped by internal BUSREQ signal. When using SR mode LCDC, programmer
need to care the CPU performance.
NOTE2) TMP92CH21 has 16KB SRAM, this internal RAM can available to use for display
RAM. Internal RAM access is very fast (32bit bus width, 1-SYSCLK read/write), disturbance
time of CPU is able to set minimum time at LCDC DMA.
This LCDC support monochrome, 2bpp (4gray), 3bpp (8gray), 4bpp (16gray), 8bpp (256 color)
and 12bpp (4096 color. Display RAM is supported external SDRAM, SRAM and internal RAM
(16KB).
It is automatically set to suitable condition data correction against interference between pixels in
panels. It doesn't need special adjustment.
In passive matrix STN mode, it support for 8 bpp (256 colors) out of a palette of 4096 colors. And
it support for 4096 color out of a pallet of 4096 colors.
Selectable data output width in 4bit or 8bit. And selectable data output sequence in 2 mode.
We'll explain about setting to control SR type LCDD from next page.
Under Development
92CH21-319
TMP92CH21
SYS.