Toshiba TLCS-900/H1 Series Data Book page 382

3.17.4.5 NAND Flash Interrupt Status Register (ND0FISR, ND1FISR)
Bit Mnemonic

7 : 1
0 RDY Ready
Figure 3.17.4(5) NAND Flash Interrupt Status Register (ND0FISR ,ND1FISR)
3.17.4.6 NAND Flash Interrupt Mask Register (ND0FIMR, ND1FIMR)
Bit Mnemonic
7 INTEN Interrupt Enable

6 : 1
0 MRDY Mask RDY
interrupt
Figure 3.17.4(6) NAND Flash Interrupt Mask Register (ND0FIMR ,ND1FIMR)
Field Name

Reserved
Ready (Default: 0)
This bit is set when NDR/B signal changes from Low(means BUSY) to High(means
READY) if NDFIMR<MRDY> is one. Writing "1" clears this bit to zero.
Read:
0: None
1: Change NDR/B signal from Busy to Ready.
Write:
0: No change
1: Clear to zero
Field Name
Interrupt Enable (Default: 0)
When <INTEN> and <MRDY> are set one and NDFISR<RDY> becomes one,
the interrupt INTNDFC occurs.
0: Disable
1: Enable

Reserved
Mask Ready Interrupt (Default: 0)
This bit masks the NDFISR<RDY> . If <MRDY> is one, NDFISR<RDY> is set
when NDR/B signal changes from Low to High.
0: Disable to set NDFISR<RDY>
1: Enable to set NDFISR<RDY>
92CH21-378
7 6 5 4
Description
7 6 4
INTEN
R/W
0
Description
TMP92CH21
3 2 1 0
RDY
3 2 1 0
0 MRDY
R/W : Type
0
: Type
: Default
: Default