Toshiba TLCS-900/H1 Series Data Book page 132

Example: To generate 1/4-duty 62.5 kHz pulses (at fsys = 20 MHz):
Calculate the value which should be set in the timer register.
To obtain a frequency of 62.5 kHz, the pulse cycle t should be: t = 1/62.5 kHz = 16 μs
φT1 = 0.4 µs (at 20 MHz);
16 µs ÷ 0.4 µs = 40
Therefore set TA1REG to 40 (28H)
The duty is to be set to 1/4: t × 1/4 = 16 µs × 1/4 = 4 µs
4 µs ÷ 0.4 µs = 10
Therefore, set TA0REG = 10 = 0AH.
7
←
TA01RUN 0
←
TA01MOD 1
←
TA0REG 0
←
TA1REG 0
←
TA1FFCR X
←
PCCR –
←
PCFC –
←
TA01RUN 1
Note: X = Don't care; "−" = No change
16 µs
6 5 4 3 2 1 0
X X X – 0 0 0
0 X X X X 0 1
0 0 0 1 0 1 0
0 1 0 1 0 0 0
X X X 0 1 1 X
– – – – – – 1
– – – – – – 1
X X X – 1 1 1
92CH21 - 128
Stop TMRA0 and TMRA1 and clear it to "0".
Set the 8-bit PPG mode, and select φT1 as input clock.
Write 0AH
Write 28H
Set TA1FF, enabling both inversion and the double buffer.
10 generates a negative logic pulse.
Set PC0 as the TA1OUT pin.
Start TMRA0 and TMRA1 counting.
TMP92CH21