Toshiba TLCS-900/H1 Series Data Book page 380

3.17.4.3 NAND Flash Mode Control Register (ND0FMCR, ND1FMCR)
Bits Mnemonic
7 WE Write Enable
6 ECC1 ECC Control
5 ECC0
4 CE Chip Enable
3 PCNT1 Power Control
2 PCNT0
Address Latch
1 ALE
Enable
0 CLE Command Latch
Enable
Figure 3.17.4(3) NAND Flash Mode Control Register (ND0FMCR ,ND1FMCR)
Field Name
Write Enable (Default: 0)
This bit enables the data write operation. When you write the data to the NAND flash,
this bit must be set one.
0: Inhibit write operation
1: Enable write operation
ECC Control (Default: 00)
These bits control the ECC calculating circuits with <CE>(bit4)-register.
11 (at <CE>=X) : Reset ECC circuits.
00 (at <CE>=1)
01 (at <CE>=1)
10 (at <CE>=1)
10 (at <CE>=0)
Chip Enable (Default: 0)
Enable NAND Flash access. This bit must be set one when access to the NAND
Flash.
0: Disable(/NDCE is high.)
1: Enable (/NDCE is low. )
Power Control (Default: 00)
11: Power On
10: Power Off
01: Power On (continue)
00: reserved
Address Latch Enable (Default: 0)
This bit specifies the value of NDALE signal.
0: Low
1: High
Command Latch Enable (Default: 0)
This bit specifies the value of NDCLE signal.
0: Low
1: High
92CH21-376
7 6 5 4
WE ECC1 ECC0 CE
R/W R/W R/W R/W
0 0 0 0
Description
: ECC circuits is disable.
: ECC circuits is enable.
: Read ECC data calculated by NDFC.
: Read ID data.
TMP92CH21
3 2 1 0
PCNT1 PCNT0 ALE CLE
R/W R/W R/W R/W : Type
0 0 0 0 : Default