Toshiba TLCS-900/H1 Series Data Book page 385

TMP92CH21
3.17.5 Timing Diagrams
3.17.5.1 Command and Address Cycle
ND0FMCR<ALE> = 0
ND0FMCR<CLE> = 0
ND0FMCR<ALE> = 1
ND0FMCR<CLE> = 1
ND0FMCR<CE> = 1
Figure 3.17.5(1) Command and Address Cycle
92CH21-381