Toshiba TLCS-900/H1 Series Data Book page 349
32bit micro controller
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TMP92CH21 has LGOE2 to LGOE0 pins to control 3kind of gate output individually. LGOE0 start
to out from rising up timing of LCP1's 1'st pulse and repeat out each 3 pulse of LCP1. LGOE1 start
to out from LCP1's 2'nd pulse, LGOE2 start to out from LCP1's 3'rd pulse. And all LGOE repeat out.
LGOE2 to LGOE0 signal can adjust 1/16 of LCP1 cycle minimum step, and that information from
48bit control register.
TFT gate driver's output can be controlled by this serious timing and can available to make
blanking adjustment and to zoom function.
LCP1
LGOEn
Before timing waveform
Setting example
LGOEn
LSB← 100000000000000110000000000000111100000000000111 →MSB
* It can make free waveform to write to 48bit register in LCDOEn5 to LCDn0
(Write to 1, high-level out and write to 0, low-level out. LSB fast)
Note) Above explanation and figure are follow setting case.
Condition: <LCDCTL2>CPHP=1,CPVP=0
In case of CPHP=0,CPVP=1 setting, LCP0 and LCP1 phase is invert
Under Development
1
2
3
4
5
Minimum division is 1/16 of "LCP1", and total 48 division
Detail waveform GOEn signal for TFT gate driver
92CH21-345
6
7
8
9 ...
TMP92CH21
After timing waveform
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