Toshiba TLCS-900/H1 Series Data Book page 106
32bit micro controller
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(6)
Basic bus timing
(a) External Read / Write Cycle (0 WAIT)
SDCLK
(20MHz)
/CSn
A23 to 0
/SRxxB
/RD
D31 to 0
/SRWR
/WRxx
D31 to 0
(b) External Read / Write Cycle (1 WAIT)
SDCLK
(20MHz)
/CSn
A23 to 0
/SRxxB
/RD
D31 to 0
/SRWR
/WRxx
D31 to 0
T1
T2
input
output
T1
TW
output
92CH21-102
read
write
T2
read
input
write
TMP92CH21
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