Toshiba TLCS-900/H1 Series Data Book page 29

3.3.4 Clock doubler (PLL)
PLL outputs the f
low-frequency oscillator, even though the internal clock is high-frequency.
A Reset initializes PLL to Stop status, setting to PLLCR0,PLLCR1-register is needed before
use.
Like an oscillator, this circuit requires time to stabilize. This is called the lock-up time and
it is measured by 16-stage binary counter. Lock-up time is about 1.6ms at f
(note-1) Input frequency limitation for PLL
(note-2) PLLCR0<LUPFG>
The following is an setting example for PLL-starting and PLL-stopping.
(example-1) PLL-starting
PLLCR0
PLLCR1
LUP:
X: Don't care
<PLLON>
<FCSEL>
PLL output: f
PLL
Lockup timer
<LUPFG>
System clock f
SYS
(example-2) PLL-stopping
PLLCR0
PLLCR1
X: Don't care
<FCSEL>
<PLLON>
PLL output: f
PLL
System clock f
SYS
clock signal, which is four times as fast as f
PLL
The limitation of input frequency(High frequency oscillation) for PLL is following.
f = 6 ~ 10MHz (Vcc = 3.0~ 3.6V)
OSCH
The logic of PLLCR0<LUPFG> is different from 900/L1's DFM.
Be careful to judge an end of lock-up time.
EQU 10E8H
EQU 10E9H
LD (PLLCR1), 1XXXXXXXXB
BIT 5, (PLLCR0)
JR Z, LUP
LD (PLLCR0), X1XXXXXXB
Counts up by f
Starts PLL operation and
Starts lock-up.
EQU 10E8H
EQU 10E9H
LD (PLLCR0), X0XXXXXXB
LD (PLLCR1), 0XXXXXXXB
Changes from 40MHz to 10 MHz.
92CH21 - 25
;
Enables PLL operation and starts lock-up
;
Detects end of lock-up
;
; Changes fc from 10 MHz to 40 MHz.
OSCH
During lock-up
Changes from 10MHz to 40 MHz.
Ends of lock-up
; Changes fc from 40 MHz to10 MHz.
; Stop PLL.
Stops PLL operation .
TMP92CH21
. It can use the
OSCH
= 10MHz.
OSCH
.
After lock-up