Toshiba TLCS-900/H1 Series Data Book page 252

32bit micro controller

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Table of Contents

(a) Single packet mode

This is data sequencein single packet mode in using CPUbusI/F.

Figure 6.1 is receivingsequence,figure 6.2 is sendingsequence.Main of this chapter is access to FIFO.

Datasequencewith USB host show chapter 5.

Endpoint 0 can't change mode by exclusive single packet mode. Shift in single packet and dual packet

of Endpoint 1-3 can changing by setting Epx_SINGLE register. Don't shift loading.

Wait to receiving data

DATASET register

・Set bit of EPx_DSET_A

・Assert EPx_DATASETsignal

DATASET register

・checkbit of EPx_DSET_A

SIZE register

・Size of SIZE_A_L confirmation

・Size of SIZE_A_Hconfirmation

RD of size to receiving data

at applicable Endpoint

・Clear receiving data in FIFO

・Clear applicable bit of DATASET register

Figure 3.10.10 Receiving sequencein single packet mode

Receiving valid data

Interrupt by EPx_FULLA

DATASET register・