Toshiba TLCS-900/H1 Series Data Book page 343

Relation of Memory map image and Output data
256 Color (8 bpp; R:3bit,G:3bit,B:2bit)
Display memory image
Address 0
LSB
D0
0 1 2 3 4 5 6
R1 G1 B1
Address 4
LSB
D0
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
R5 G5 B5
LD bus output sequence
8bit (TFT)
LD0 0(R1) to 8(R2) ~
LD1 1(R1) to 9(R2) ~
LD2 2(R1) to 10(R2) ~
LD3 3(G1) to 11(G2) ~
LD4 4(G1) to 12(G2) ~
LD5 5(G1) to 13(G2) ~
LD6 6(B1) to 14(B2) ~
LD7 7(B1) to 15(B2) ~
*When use 256 color TFT mode, it need to use 8bit LD bus width.
LD8,LD9,LD10 and LD11 terminals can available to use for general port.
Under Development
Address 1
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R2 G2 B2
Address 5
R6 G6 B6
Relation of Memory map image and Output data (5)
92CH21-339
Address 2
R3 G3 B3
Address 6
R7 G7 B7
TMP92CH21
Address 3
MSB
D31
R4 G4 B4
Address 7
MSB
D31
R8 G8 B8