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Toshiba TXZ Reference Manual

32-bit risc microcontroller
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TXZ Family
Flash Memory
32-bit RISC Microcontroller
TXZ Family
Reference Manual
Flash Memory
(Code Flash: 1.5MB/1.0MB/768KB/512KB)
(Data: Flash 32KB)
(FLASH15MHD32-A)
Revision 2.0
2018-06
1 / 120
2018-06-05
Rev. 2.0
© 2018
Toshiba Electronic Devices & Storage Corporation

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  • Page 1 TXZ Family Flash Memory 32-bit RISC Microcontroller TXZ Family Reference Manual Flash Memory (Code Flash: 1.5MB/1.0MB/768KB/512KB) (Data: Flash 32KB) (FLASH15MHD32-A) Revision 2.0 2018-06 1 / 120 2018-06-05 Rev. 2.0 © 2018 Toshiba Electronic Devices & Storage Corporation...

  • Page 2: Table Of Contents

    TXZ Family Flash Memory Contents Preface ................................. 8 Related documents ..............................8 Conventions ................................9 Terms and Abbreviation ............................11 Outline ................................. 12 Memory map ..............................14 Configuration ............................... 15 Block Diagrams ..............................15 Configuration of Code Flash ..........................16 2.2.1.
  • Page 3 TXZ Family Flash Memory 3.3.5. Memory Swap................................49 Details of Flash Memory ..........................51 Functions................................51 4.1.1. Operation Mode of the Flash Memory ........................52 4.1.2. Command Execution ..............................52 4.1.3. Command Description ..............................54 4.1.3.1. Automatic Programming ..............................54 4.1.3.2.
  • Page 4 TXZ Family Flash Memory 5.2.5. [FCPSR0] (Flash Protect Status Register 0) ......................69 5.2.6. [FCPSR1] (Flash Protect Status Register 1) ......................70 5.2.7. [FCPSR3] (Flash Protect Status Register 3) ......................71 5.2.8. [FCPSR4] (Flash Protect Status Register 4) ......................71 5.2.9.
  • Page 5 TXZ Family Flash Memory 6.6.6. Common Operation Regardless of the Command ...................... 93 6.6.6.1. Serial Operation Mode Determination ........................... 93 6.6.6.2. Acknowledgement Response Data ..........................95 6.6.6.3. Password ..................................96 6.6.6.4. Password Determination ............................... 99 6.6.6.5. CHECKSUM Calculation ............................... 99 6.6.7.
  • Page 6 TXZ Family Flash Memory List of Figures Figure 1.1 The example of a memory map ....................14 Figure 2.1 The Block Diagrams of a flash memory.................. 15 Figure 3.1 Flowchart of automatic programming (1) ................41 Figure 3.2 Flowchart of automatic programming (2) ................42 Figure 3.3 Flowchart of automatic erasing (1) ..................
  • Page 7 TXZ Family Flash Memory List of Tables Table 1.1 Functional description (code flash) ..................12 Table 1.2 Functional description (user information area) ................ 13 Table 1.3 Functional description (data flash) ................... 13 Table 2.1 Signal list ..........................15 Table 2.2 Block Configuration of 1536KB code flash ................16 Table 2.3 Block Configuration of 1024KB code flash ................

  • Page 8: Preface

    TXZ Family Flash Memory Preface Related documents Document name Clock Control and Operation Mode Exception Input/Output Ports Product Information Asynchronous Serial Communication Circuit 8 / 120 2018-06-05 Rev. 2.0...

  • Page 9: Conventions

    TXZ Family Flash Memory Conventions ● Numeric formats follow the rules as shown below: Hexadecimal: 0xABC Decimal: 123 or 0d123 – Only when it needs to be explicitly shown that they are decimal numbers. Binary: 0b111 – It is possible to omit the “0b” when the number of bit can be distinctly understood from a sentence.
  • Page 10 TXZ Family Flash Memory *********************************************************************************************************************** Arm, Cortex and Thumb are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. All rights reserved. *********************************************************************************************************************** The flash memory uses the Super Flash® technology under the license of Silicon Storage Technology, Inc.

  • Page 11: Terms And Abbreviation

    TXZ Family Flash Memory Terms and Abbreviation Some of abbreviations used in this document are as follows: Acknowledgement Addr Address Address Block Kilo Bytes Page Power On Reset Special Function Register UART Universal Asynchronous Receiver Transmitter 11 / 120 2018-06-05...

  • Page 12: Outline

    TXZ Family Flash Memory 1. Outline The code flash which stores a program code, and the data flash which stores data are explained. A code flash stores an instruction code, and CPU reads and executes it. There is user information area which can be accessed in a code flash by bank change. Since user information area is not erased by a chip erasing command, for example, it can be written a unique management number etc.

  • Page 13: Table 1.2 Functional Description (User Information Area)

    TXZ Family Flash Memory Table 1.2 Functional description (user information area) Function Flash memory Function Functional Description Comments classification Automatic Data programming is performed Programming at 4 words (16 bytes). Programming and Erasing all the User information Erasing Automatic page area is performed automatically.

  • Page 14: Memory Map

    TXZ Family Flash Memory Memory map 0xFFFFFFFF 0x5E180000 Flash domain (Mirror) Code Flash CODE FLASH CODE FLASH Programming/ Erasing/ (Mirror 1536KB) (Mirror 1536KB) Read 0x5E000000 FLASH (SFR) FLASH (SFR) フラッシュ(SFR) 0x5DFF0000 0x3F7F9800 BOOT ROM BOOT ROM 0x3F7F8000 (Mirror) Flash domain (Data)

  • Page 15: Configuration

    TXZ Family Flash Memory 2. Configuration Block Diagrams The Block Diagrams of a Flash memory and a signal list are shown. INTFLCRDY1 INTFLCRDY0 Code Flash interface0 (FLASH I/F0) Flash Status Register 0 Code Flash interface1 [FCSR0] (FLASH I/F1) Read buffer...

  • Page 16: Configuration Of Code Flash

    TXZ Family Flash Memory Configuration of Code Flash 2.2.1. Unit of the composition There are "Area", "Block", and "Page" as a unit of the composition of a code flash. Area  It is used by an erase function. One area size is a maximum of 512 KB. It changes with memory sizes of a product.
  • Page 17 TXZ Family Flash Memory Block18 0x00090000-0x00097FFF 0x5E090000-0x5E097FFF Block19 0x00098000-0x0009FFFF 0x5E098000-0x5E09FFFF Block20 0x000A0000-0x000A7FFF 0x5E0A0000-0x5E0A7FFF Block21 0x000A8000-0x000AFFFF 0x5E0A8000-0x5E0AFFFF Block22 0x000B0000-0x000B7FFF 0x5E0B0000-0x5E0B7FFF Block23 0x000B8000-0x000BFFFF 0x5E0B8000-0x5E0BFFFF Block24 0x000C0000-0x000C7FFF 0x5E0C0000-0x5E0C7FFF Block25 0x000C8000-0x000CFFFF 0x5E0C8000-0x5E0CFFFF Block26 0x000D0000-0x000D7FFF 0x5E0D0000-0x5E0D7FFF Block27 0x000D8000-0x000DFFFF 0x5E0D8000-0x5E0DFFFF Block28 0x000E0000-0x000E7FFF 0x5E0E0000-0x5E0E7FFF Block29 0x000E8000-0x000EFFFF 0x5E0E8000-0x5E0EFFFF...

  • Page 18: Table 2.3 Block Configuration Of 1024Kb Code Flash

    TXZ Family Flash Memory Table 2.3 Block Configuration of 1024KB code flash FLASH Program/erase/read Block size Area Block name Code execution address address (KB) 0x00000000-0x00000FFF 0x5E000000-0x5E000FFF 0x00001000-0x00001FFF 0x5E001000-0x5E001FFF 0x00002000-0x00002FFF 0x5E002000-0x5E002FFF 0x00003000-0x00003FFF 0x5E003000-0x5E003FFF Block0 0x00004000-0x00004FFF 0x5E004000-0x5E004FFF 0x00005000-0x00005FFF 0x5E005000-0x5E005FFF 0x00006000-0x00006FFF 0x5E006000-0x5E006FFF 0x00007000-0x00007FFF...

  • Page 19: Table 2.4 Block Configuration Of 768Kb Code Flash

    TXZ Family Flash Memory Table 2.4 Block Configuration of 768KB code flash FLASH Program/erase/read Block size Area Block name Code execution address address (KB) 0x00000000-0x00000FFF 0x5E000000-0x5E000FFF 0x00001000-0x00001FFF 0x5E001000-0x5E001FFF 0x00002000-0x00002FFF 0x5E002000-0x5E002FFF 0x00003000-0x00003FFF 0x5E003000-0x5E003FFF Block0 0x00004000-0x00004FFF 0x5E004000-0x5E004FFF 0x00005000-0x00005FFF 0x5E005000-0x5E005FFF 0x00006000-0x00006FFF 0x5E006000-0x5E006FFF 0x00007000-0x00007FFF...

  • Page 20: Table 2.5 Block Configuration Of 512Kb Code Flash

    TXZ Family Flash Memory Table 2.5 Block Configuration of 512KB code flash FLASH Program/erase/read Block size Area Block name Code execution address address (KB) 0x00000000-0x00000FFF 0x5E000000-0x5E000FFF 0x00001000-0x00001FFF 0x5E001000-0x5E001FFF 0x00002000-0x00002FFF 0x5E002000-0x5E002FFF 0x00003000-0x00003FFF 0x5E003000-0x5E003FFF Block0 0x00004000-0x00004FFF 0x5E004000-0x5E004FFF 0x00005000-0x00005FFF 0x5E005000-0x5E005FFF 0x00006000-0x00006FFF 0x5E006000-0x5E006FFF 0x00007000-0x00007FFF...

  • Page 21: Page Configuration

    TXZ Family Flash Memory 2.2.3. Page Configuration Table 2.6 to Table 2.9 show example of page configuration code flash. Table 2.6 Page Configuration of 1536KB code flash FLASH Page size Area Page name Code execution address Program/erase/read address (KB) Page0...

  • Page 22: Table 2.7 Page Configuration Of 1024Kb Code Flash

    TXZ Family Flash Memory Table 2.7 Page Configuration of 1024KB code flash FLASH Page size Area Page name Code execution address Program/erase/read address (KB) Page0 0x00000000-0x00000FFF 0x5E000000-0x5E000FFF Page1 0x00001000-0x00001FFF 0x5E001000-0x5E001FFF Page2 0x00002000-0x00002FFF 0x5E002000-0x5E002FFF Page3 0x00003000-0x00003FFF 0x5E003000-0x5E003FFF Page4 0x00004000-0x00004FFF 0x5E004000-0x5E004FFF Page5...

  • Page 23: Table 2.8 Page Configuration Of 768Kb Code Flash

    TXZ Family Flash Memory Table 2.8 Page Configuration of 768KB code flash FLASH Page size Area Page name Code execution address Program/erase/read address (KB) Page0 0x00000000-0x00000FFF 0x5E000000-0x5E000FFF Page1 0x00001000-0x00001FFF 0x5E001000-0x5E001FFF Page2 0x00002000-0x00002FFF 0x5E002000-0x5E002FFF Page3 0x00003000-0x00003FFF 0x5E003000-0x5E003FFF Page4 0x00004000-0x00004FFF 0x5E004000-0x5E004FFF Page5...

  • Page 24: User Information Area Configuration Of Code Flash

    TXZ Family Flash Memory Table 2.9 Page Configuration of 512KB code flash FLASH Page size Area Page name Code execution address Program/erase/read address (KB) Page0 0x00000000-0x00000FFF 0x5E000000-0x5E000FFF Page1 0x00001000-0x00001FFF 0x5E001000-0x5E001FFF Page2 0x00002000-0x00002FFF 0x5E002000-0x5E002FFF Page3 0x00003000-0x00003FFF 0x5E003000-0x5E003FFF Page4 0x00004000-0x00004FFF 0x5E004000-0x5E004FFF Page5...

  • Page 25: Memory Capacity And The Configuration

    TXZ Family Flash Memory 2.2.6. Memory Capacity and the Configuration Table 2.11 Memory capacity and the configuration Programming Erasing time (Note1) Area Block Page time (Note1) Capacity (KB) Size Size Size Word Chip Area Page Block Area (Note2) (Note3) (KB)

  • Page 26: Configuration Of Data Flash

    TXZ Family Flash Memory Configuration of Data Flash 2.3.1. Unit of the composition There are "Area", "Block", and "Page" as a unit of the composition of a data flash. Area  It is used by an erase function. One area size is a maximum of 32 KB. It changes with memory sizes of a product.

  • Page 27: Page Configuration

    TXZ Family Flash Memory 2.3.3. Page Configuration Table 2.13 shows example page configuration of 32KB data flash. Table 2.13 Page Configuration of 32KB data flash FLASH Page size Area Page name Program/erase/read address (Byte) Page0 0x30000000-0x300000FF Page1 0x30000100-0x300001FF Page2 0x30000200-0x300002FF...

  • Page 28: Program/Erase Time Of Data Flash

    TXZ Family Flash Memory 2.3.4. Program/Erase Time of Data Flash Programming is performed in the unit of 4 bytes (1 word). Erasing is performed in the unit of Page, Block, Area, or on entire chip. An erase time varies depending on the command to be used.

  • Page 29: Function Description And Functional Explanations

    TXZ Family Flash Memory 3. Function Description and Functional Explanations Code flash and data flash are generally compliant with the JEDEC standards except for some specific functions. Therefore, if a user is currently using a Flash memory as an external memory, it is easy to implement the functions into this device.

  • Page 30: Code Flash

    TXZ Family Flash Memory Code Flash 3.1.1. Command Sequence 3.1.1.1. List of Command Sequence This section shows addresses and data of the bus write cycle in each command of code flash. Except the 5 bus cycle of ID-Read command, all cycles are “bus write cycles”. A bus write cycle is performed by a 32-bit (1 word) data transfer instruction.
  • Page 31 TXZ Family Flash Memory Sequence cycle cycle cycle cycle cycle cycle cycle Address Address Address Address Address Address Address Data Data Data Data Data Data Data Command 0xYYYYX55X 0xYYYYXAAX 0xYYYYX55X 0xYYYYX55X 0xYYYYXAAX PBA(Note) Automatic protect bit 0xAA 0x55 0x80 0xAA...

  • Page 32: Address Bit Configuration In The Bus Write Cycle (Code Flash)

    TXZ Family Flash Memory 3.1.1.2. Address Bit Configuration in the Bus Write Cycle (Code Flash) Please refer to “Table 3.3 Address bit configuration in the bus write cycle (Code flash)” with “Table 3.2 Flash memory access using the internal CPU (code flash)”.
  • Page 33 TXZ Family Flash Memory [Automatic block erasing] Address [31:24] [23:21] [20:19] [18:15] [14:0] Block address (address setting of the 6 bus write cycle of block erasing command) Area Block erasing 0:00 “000” "0” Block 0x5E 1:01 address fixed Recommended 2:10...

  • Page 34: Area Address (Aa), Block Address (Ba): Code Flash

    TXZ Family Flash Memory [Automatic security bit programming/erasing] Address [31:24] [23:19] [18:17] [16:12] [11:0] SBA: Address of the 6 bus write cycle of security bit erasing Security bit “00000” “00” “00001” "0” Erasing 0x5E fixed fixed fixed Recommended SBA: Address of...
  • Page 35 TXZ Family Flash Memory 72 to 79 <BLK9> 0x5E002100 80 to 87 <BLK10> 0x5E002110 88 to 95 <BLK11> 0x5E002120 96 to 103 <BLK12> 0x5E002130 104 to 111 <BLK13> 0x5E002140 112 to 119 <BLK14> 0x5E002150 120 to 127 <BLK15> 0x5E002160 128 to 135 <BLK16>...

  • Page 36: Id-Read Code (Ia, Id): Code Flash

    TXZ Family Flash Memory 88 to 95 <BLK11> 0x5E102120 96 to 103 <BLK12> 0x5E102130 104 to 111 <BLK13> 0x5E102140 112 to 119 <BLK14> 0x5E102150 120 to 127 <BLK15> 0x5E102160 Note: Block0 is a generic name for PG0 to PG7. 3.1.1.5. ID-Read Code (IA, ID): Code Flash “Table 3.5 ID-Read Command code assignment and the code contents”...

  • Page 37: Data Flash

    TXZ Family Flash Memory Data Flash 3.2.1. Command Sequence 3.2.1.1. List of Command Sequence This section shows addresses and data of the bus write cycle in each command of data flash. Except the 5 bus cycle of ID-Read command, all cycles are “bus write cycles”. A bus write cycle is performed by a 32-bit (1 word) data transfer instruction.

  • Page 38: Address Configuration In The Bus Write Cycle (Data Flash)

    TXZ Family Flash Memory Supplementary explanation IA: ID address ID: ID data output PGA: Page address BA: Block address AA: Area address PA: Program address (write) PD: Program data (32-bit data) PBA: Protect bit address 3.2.1.2. Address Configuration in the Bus Write Cycle (Data Flash) Please refer to “Table 3.8 Address bit configuration in the bus write cycle (data flash)”...

  • Page 39: Area Address (Aa), Block Address (Ba)

    TXZ Family Flash Memory [Automatic block erasing] Address [31:24] [23:16] [15] [14:12] [11:0] BA: Block Address (address setting of 6 bus write cycle of block erasing command) Block “00000000” "0” Area Block erasing 0x30 (Note) address fixed Recommended Note: Use “Area” fixed to “0”.

  • Page 40: Protect Bit Assignment (Pba)

    TXZ Family Flash Memory 3.2.1.4. Protect Bit Assignment (PBA) A protect bit can be controlled in the unit of one bit. “Table 3.9 Protect bit program address (Data flash)” shows the protect bit selection of the automatic protect bit program.

  • Page 41: Flowchart

    TXZ Family Flash Memory Flowchart This section shows examples of code flash programming. 3.3.1. Automatic Programming Start [FCSR0] <RDYBSY>=1？ Specify the target area of Flash memory by [FCAREASEL]<AREAn> [FCAREASEL] <SSFn> ？ Automatic programming command sequence (Refer to Figure 3.2) [FCSR0] <RDYBSY>=0？...

  • Page 42: Figure 3.2 Flowchart Of Automatic Programming (2)

    TXZ Family Flash Memory Automatic programming command sequence (address/command) (Example of Area0 Block0 to 31) 0x5E000550/0x000000AA 0x5E000AA0/0x00000055 0x5E000550/0x000000A0 Program address/ Program data (32-bit data) Program address/ Program data (32-bit data) Program address/ Program data (32-bit data) Program address/ Program data (32-bit data) Figure 3.2 Flowchart of automatic programming (2)

  • Page 43: Automatic Erasing

    TXZ Family Flash Memory 3.3.2. Automatic Erasing Start [FCSR0] <RDYBSY>=1？ Specify the target area of Flash memory by [FCAREASEL]<AREAn> [FCAREASEL] <SSFn>=1？ Command sequence: Automatic chip erasing, automatic block erasing, automatic page erasing, automatic area erasing or automatic code area erasing.

  • Page 44: Figure 3.4 Flowchart Of Automatic Erasing (2)

    TXZ Family Flash Memory Automatic block erasing command Automatic page erasing sequence command sequence Automatic chip erasing Example of Area0 Block1 to 31 Example of Area0 Page0 to 255 command sequence (address/command) (address/command) (address/command) 0x5E000550/0x000000AA 0x5E000550/0x000000AA 0x5E000550/0x000000AA 0x5E000AA0/0x00000055 0x5E000AA0/0x00000055 0x5E000AA0/0x00000055...

  • Page 45: Protect Bit

    TXZ Family Flash Memory 3.3.3. Protect bit Start [FCSR0] <RDYBSY>=1？ Set protect bit of page/block by [FCPMRm] <MSKn>(Note1) Specify the target FLASH I/F (Note2) of Flash memory by [FCAREASEL]<AREAn> [FCAREASEL] <SSFn> ？ Automatic protect bit programming command sequence, Automatic protect bit erasing command sequence (Refer to Figure 3.6)

  • Page 46: Figure 3.6 Flowchart Of Protect (2)

    TXZ Family Flash Memory Automatic protect bit programming command Automatic protect bit erasing command Example of FLASH I/F0 sequence Example of FLASH I/F0 sequence (address/command) (address/command) 0x5E000550/0x000000AA 0x5E000550/0x000000AA 0x5E000AA0/0x00000055 0x5E000AA0/0x00000055 0x5E000550/0x0000009A 0x5E000550/0x00000080 Protect bit Address / 0x0000009A 0x5E000550/0x000000AA 0x5E000AA0/0x00000055 Protect bit Address /0x00000060 Figure 3.6 Flowchart of protect (2)

  • Page 47: Security Bit

    TXZ Family Flash Memory 3.3.4. Security bit Start [FCSR0] <RDYBSY>=1？ Set [FCBMR]<SMB> Select AERA0 by [FCAREASEL]<AREA0> [FCAREASEL] <SSFn> ？ Automatic security bit programming command sequence, Automatic security bit erasing command sequence (Refer to figure 3.8) [FCSR0] <RDYBSY>=0？ [FCSR0] <RDYBSY>=1？ Release AREA0 by [FCAREASEL]<AREA0>...

  • Page 48: Figure 3.8 Flowchart Of Security (2)

    TXZ Family Flash Memory Automatic security erasing Automatic security programming command sequence command sequence (address/command) (address/command) 0x5E000550/0x000000AA 0x5E000550/0x000000AA 0x5E000AA0/0x00000055 0x5E000AA0/0x00000055 0x5E000550/0x0000009A 0x5E000550/0x00000080 0x5E001000/0x0000009A 0x5E000550/0x000000AA 0x5E000AA0/0x00000055 0x5E001000/0x00000060 Figure 3.8 Flowchart of security (2) 48 / 120 2018-06-05 Rev. 2.0...

  • Page 49: Memory Swap

    TXZ Family Flash Memory 3.3.5. Memory Swap Start [FCSR0] <RDYBSY>=1？ Specify the target FLASH I/F (Note) of Flash memory by [FCAREASEL]<AREAn> [FCAREASEL] <SSFn> ？ Automatic memory swap programming command sequence, Automatic memory swap erasing command sequence (Refer to Figure 3.10) [FCSR0] <RDYBSY>=0？...

  • Page 50: Figure 3.10 Flowchart Of Memory Swap (2)

    TXZ Family Flash Memory Automatic memory swap erasing Automatic memory swap programming Example of FLASH I/F0 command sequence command sequence Example of FLASH I/F0 (address/command) (address/command) 0x5E000550/0x000000AA 0x5E000550/0x000000AA 0x5E000AA0/0x00000055 0x5E000AA0/0x00000055 0x5E000550/0x0000009A 0x5E000550/0x00000080 Memory Swap Address/0x0000009A 0x5E000550/0x000000AA 0x5E000AA0/0x00000055 Memory Swap Address/0x00000060 Figure 3.10 Flowchart of memory swap (2)

  • Page 51: Details Of Flash Memory

    TXZ Family Flash Memory 4. Details of Flash Memory Flash memory is Programmed/erased data by executing a command in the control program. This programming/ erasing control program must be prepared by users in advance. While a program is executing on a memory in FLASH I/F0, an other memory region in FLASH I/F (for example, FLASH I/F2<Area 4>: Data Flash memory) can be erased or written if the latter memory does not operate (and vice...

  • Page 52: Operation Mode Of The Flash Memory

    TXZ Family Flash Memory 4.1.1. Operation Mode of the Flash Memory The flash memory has three main operation modes: Read the memory data (Read mode) Input command for erasing/programming (Command sequence input mode) Erase/program data automatically (Automatic operation mode) After power-on, or after reset, the flash memory enters read mode if the automatic operation is properly completed.
  • Page 53 TXZ Family Flash Memory Automatic chip erasing command  ID-Read command  Automatic security bit programming command  Automatic security bit erasing command  Automatic protect bit programming command  Automatic protect bit erasing command  Automatic memory swap command ...

  • Page 54: Command Description

    TXZ Family Flash Memory 4.1.3. Command Description This section explains each command contents. For details of specific command sequences, refer to “3.1.1Command Sequence” and “3.2.1Command Sequence”. 4.1.3.1. Automatic Programming (1) Operation Code flash can be programmed in four words (16 bytes) unit with the automatic programming command sequence.

  • Page 55: Automatic Chip Erasing

    TXZ Family Flash Memory 4.1.3.2. Automatic chip erasing (1) Operation Automatic chip erasing erases memory cells in all addresses. It erases in order of a data flash and a code flash. If protected pages or blocks are contained, the automatic chip erasing is performed on unprotected pages or blocks (Note1).

  • Page 56: Automatic Block Erasing

    TXZ Family Flash Memory 4.1.3.4. Automatic Block Erasing (1) Operation The automatic block erasing command performs on the specified block. If protected pages or blocks are contained, the automatic block erasing is not performed on these pages or blocks. And flash memory returns to command sequence input mode.

  • Page 57: Automatic Protect Bit Erasing

    TXZ Family Flash Memory 4.1.3.7. Automatic Protect Bit Erasing (1) Operation The automatic protect bit erasing command erase the protect bit regardless of the security state of the flash memory. For details of the protection function, refer to “4.1.6Protection Function”.

  • Page 58: Automatic Security Bit Erasing

    TXZ Family Flash Memory 4.1.3.9. Automatic Security Bit Erasing (1) Operation The operation of the automatic security bit erasing command varies depending on the security state of the flash memory. Non secured state Erase the security bit. Security state Erase all address of code flash and data flash, and erase security bit.

  • Page 59: Read/Reset Command

    TXZ Family Flash Memory 4.1.3.11. Read/Reset Command (1) Operation This command is to return the flash memory to read mode. (2) How to set The 1 bus write cycle is the Read/Reset command sequence. After the command sequence is executed, the flash memory returns to read mode.

  • Page 60: Stopping Automatic Chip Erasing

    TXZ Family Flash Memory 4.1.4. Stopping Automatic Chip Erasing When the user attempts to cancel the automatic chip erasing in the middle of the process, cancel the automatic chip erasing as follows: The flash memory returns to read mode. 1. Read [FCSR0]<RDYBSY>.

  • Page 61: Protection Function

    TXZ Family Flash Memory 4. When you do not program in continuously, in an interrupt handler, INTFLDRDY interruption is disabled, and perform return. When you program in continuously, issue a new command sequence after INTFLDRDY interruption without disable, and perform return.

  • Page 62: Security Function

    TXZ Family Flash Memory 4.1.7. Security Function The security function can disable data reading from the flash writer, and disable the debug function. 4.1.7.1. Security Setting In order to enable a security function, a security bit is set to “1” by a security bit program command.

  • Page 63: Memory Swap Function

    TXZ Family Flash Memory 4.1.8. Memory Swap Function When application program reprogramming on the code flash is suspended, the power may become off after the program code is erased, and application program reprogramming may not be continued. To avoid such case, use this memory swap function to save your program.

  • Page 64: Erasing The Memory Swap Information

    TXZ Family Flash Memory 5. Program new data to the blank region. Page0: Copied data (Old original data) Page1: New original data 6. Release the swap state. Page0: New original data Page1: Copied data (Old original data) 7. Execute the automatic protect bit erasing command.

  • Page 65: User Information Area

    TXZ Family Flash Memory 4.1.9. User Information Area Instructions cannot be executed in the user information area. Data reading can be instructed by the CPU. Data becomes accessible on bank switching with [FCBNKCR]. For address assignment, refer to “Table 2.10 User Information Area Configuration of Code Flash”.

  • Page 66: Registers

    TXZ Family Flash Memory 5. Registers Register List The table below lists the registers related to flash memory. Base address Circumference function channel/unit Type 1 Flash Memory 0x5DFF0000 (Base+) Register name Address Flash Security Bit Mask Register 0x0010 [FCSBMR] Flash Security Status Register...

  • Page 67: Detail Of Register

    TXZ Family Flash Memory Detail of Register 5.2.1. [FCSBMR] (Flash Security Bit Mask Register) Bit Symbol Type After reset Function 31:1 Read as "0" Security mask bit 1: No masked 0: Masked (Security is temporarily released) When security is enabled ([FCSSR]<SEC>= 1), if “0” is written to this register, security is temporarily released.

  • Page 68: Fcsr0] (Flash Status Register 0)

    TXZ Family Flash Memory 5.2.4. [FCSR0] (Flash Status Register 0) Bit Symbol Type After reset Function 31:16 Read as “0” undefined Read as “undefined value” 14:11 Read as “0” ReadyBusy flag of Area 4 RDYBSY2 0: In automatic operation 1: Completion of automatic operation...

  • Page 69: Fcpsr0] (Flash Protect Status Register 0)

    TXZ Family Flash Memory 5.2.5. [FCPSR0] (Flash Protect Status Register 0) Bit Symbol Type After reset Function 31:8 Read as “0” Protect status of code flash (Area 0). 1: Protected 0: Not protected This register indicates the protected status of each page from Page0 to Page7 (Block0).

  • Page 70: Fcpsr1] (Flash Protect Status Register 1)

    TXZ Family Flash Memory 5.2.6. [FCPSR1] (Flash Protect Status Register 1) Bit Symbol Type After reset Function BLK31 BLK30 BLK29 BLK28 BLK27 BLK26 BLK25 BLK24 BLK23 BLK22 BLK21 BLK20 BLK19 Protect status of code flash (Area 0,1). BLK18 1: Protected...

  • Page 71: Fcpsr3] (Flash Protect Status Register 3)

    TXZ Family Flash Memory 5.2.7. [FCPSR3] (Flash Protect Status Register 3) Bit Symbol Type After reset Function 31:8 Read as “0” Protect status of code flash (Area 2). 1: Protected 0: Not protected This register indicates the protected status of each page from Page0 to Page7 (Block0).

  • Page 72: Fcpsr6] (Flash Protect Status Register 6)

    TXZ Family Flash Memory 5.2.9. [FCPSR6] (Flash Protect Status Register 6) Bit Symbol Type After reset Function 31:8 Read as “0” DBLK7 Protect status of data flash (Area 4). DBLK6 1: Protected DBLK5 0: Not protected DBLK4 This register indicates the protected status of each block of DBLK3 data flash.

  • Page 73: Fcpmr1] (Flash Protect Mask Register 1)

    TXZ Family Flash Memory 5.2.11. [FCPMR1] (Flash Protect Mask Register 1) Bit Symbol Type After reset Function MSK31 MSK30 MSK29 MSK28 MSK27 MSK26 MSK25 MSK24 MSK23 MSK22 MSK21 MSK20 MSK19 MSK18 Protect mask status of code flash (Area 0,1). 1: Not masked (Protected)

  • Page 74: Fcpmr3] (Flash Protect Mask Register 3)

    TXZ Family Flash Memory 5.2.12. [FCPMR3] (Flash Protect Mask Register 3) Bit Symbol Type After reset Function 31:8 Read as “0” Protect mask status of code flash (Area 2). 1: Not masked (Protected) 0: Masked (Not protected) This register masks each protected page from Page0 to Page7 (block0).

  • Page 75: Fcpmr4] (Flash Protect Mask Register 4)

    TXZ Family Flash Memory 5.2.13. [FCPMR4] (Flash Protect Mask Register 4) Bit Symbol Type After reset Function 31:16 Write as “1” MSK15 MSK14 MSK13 MSK12 MSK11 MSK10 Protect mask status of code flash (Area 2). 1: Not masked (Protected) MSK9...

  • Page 76: Fcpmr6] (Flash Protect Mask Register 6)

    TXZ Family Flash Memory 5.2.14. [FCPMR6] (Flash Protect Mask Register 6) Bit Symbol Type After reset Function 31:16 Read as “0” 15:8 Write as “1” DMSK7 Protect status of data flash (Area 4). DMSK6 1: Not masked (Protected) DMSK5 0: Masked (Not protected)

  • Page 77: Fcswpsr] (Flash Memory Swap Status Register)

    TXZ Family Flash Memory 5.2.16. [FCSWPSR] (Flash Memory SWAP Status Register) Bit Symbol After reset Type Function 31:14 Read as “0” This bit indicates the setting of memory swap size (Area 0). 000000: No swap (Initial value) 000001: 4K bytes (Page0  Page1) 000010: 8K bytes (Page0 to 1 ...

  • Page 78: Fcareasel] (Flash Area Selection Register)

    TXZ Family Flash Memory 5.2.17. [FCAREASEL] (Flash Area Selection Register) Bit Symbol Type After reset Function Read as “0” Selection of Area 4 SSF4 1: Selects Area 4 (Data write mode) 0: Not select Area 4 (Data read mode) Read as “0”...

  • Page 79: Fccr] (Flash Control Register)

    TXZ Family Flash Memory Note2: To rewrite this register, follow the procedure below: 1. Write the specific code (0xA74A9D23) to [FCKCR]. 2. Rewrite the data of [FCAREASEL]<AREAn> within 16 clocks after the previous action. Note3: Rewrite the contents of this register on the program code in the RAM.

  • Page 80: Fcbnkcr] (Flash Bank Change Register)

    TXZ Family Flash Memory 5.2.20. [FCBNKCR] (Flash Bank Change Register) Bit Symbol Type After reset Function 31:7 Read as “0” Write as “000” Read as “0” Address “0x5E005000” to “0x5E005FFF” of code flash change to the user information area. BANK0[2:0]...

  • Page 81: The Programming Method

    TXZ Family Flash Memory 6. The programming method Initialization Before performing programming/erasing operation to a code flash or a data flash, must be oscillate a internal high speed oscillator1 (IHOSC1). And. Please operate flash memory after oscillation start and check [CGOSCCR]<IHOSC1F>=1.

  • Page 82: Mode Determination

    TXZ Family Flash Memory Mode Determination The transition destination is determined by the status of RESET_N pin or the status of BOOT_N pin at deassertion of Power On Reset (POR). Table 6.2 Operation mode setting Operation mode RESET_N BOOT_N Single chip mode 0 ...

  • Page 83: 1-A) Procedure That A Programming Routine Stored In Flash Memory

    TXZ Family Flash Memory 6.5.1. (1-A) Procedure that a Programming Routine Stored in Flash memory 6.5.1.1. Step-1 A user determines the conditions (e.g., pin status) to enter the user boot mode and the I/O to be used to transfer data.

  • Page 84: Step-2

    TXZ Family Flash Memory 6.5.1.2. Step-2 This section explains the case that a programming routine stored in the reset service routine. First, the reset routine determines to enter the user boot mode. If mode switching conditions are met, the device enters the user boot mode to reprogram data.

  • Page 85: Step-4

    TXZ Family Flash Memory 6.5.1.4. Step-4 The device jumps to the programming routine (c) on the RAM to release the program/erase protection for the old application program, and to erase the flash (the units of erase is arbitrary size). (c) Programming routine...

  • Page 86: Step-6

    TXZ Family Flash Memory 6.5.1.6. Step-6 Upon reset, the flash memory is set to normal mode. After reset, the CPU will start operation along with the new application program. (Note) (b) Copy routine (c) Programming routine Figure 6.6 Procedure that a Programming Routine Stored in Flash memory (6) Note: All products do not support the determination of the transition destination by the deassertion of Power On Reset (POR).

  • Page 87: Step-2

    TXZ Family Flash Memory 6.5.2.2. Step-2 This section explains the case where a programming routine is stored in the reset service routine. First, the reset service routine determines to enter user boot mode. If mode switching conditions are met, the device enters user boot mode to reprogram data.

  • Page 88: Step-4

    TXZ Family Flash Memory 6.5.2.4. Step-4 The device jumps to the programming routine on the RAM to release the program/erase protection for the old application program, and to erase the flash (the units of erase is arbitrary size). Figure 6.10 Procedure that a Programming Routine is Transferred from External Host (4) 6.5.2.5.

  • Page 89: Step-6

    TXZ Family Flash Memory 6.5.2.6. Step-6 The flash memory is set to normal mode by reset. After reset, the CPU will start operation along with the new application program. 0 1 RESET_N (Note) Figure 6.12 Procedure that a Programming Routine is Transferred from External Host (6) Note: All products do not support the determination of the transition destination by the deassertion of Power On Reset (POR).

  • Page 90: How To Reprogram The Flash In Single Boot Mode

    Memory swap bits Security bit UART (Note) of a target (TXZ microcontroller) and the external host controller (hereafter controller) are connected. The "flash reprogramming program" sent from the controller is stored in on-chip RAM. The “flash reprogramming program” on RAM is run, and a flash memory is reprogrammed.

  • Page 91: Mode Setting

    TXZ Family Flash Memory 6.6.2. Mode Setting In order to execute the on-board programming, boot up this device in single boot mode. For details of single boot mode setting, refer to “6.3 Mode Determination”. 6.6.3. Interface Specifications This section describes the serial communication format in single boot mode. The serial operation mode supports UART (asynchronous communication).

  • Page 92: Restrictions On Memories

    TXZ Family Flash Memory 6.6.4. Restrictions on Memories Note that the single boot mode places restrictions on the on-chip RAM and on-chip flash memory as shown in “Table 6.5 Restrictions on the memories in single boot mode”. Table 6.5 Restrictions on the memories in single boot mode...

  • Page 93: Common Operation Regardless Of The Command

    TXZ Family Flash Memory 6.6.6. Common Operation Regardless of the Command This section describes common operation under the boot program execution condition. 6.6.6.1. Serial Operation Mode Determination The controller must send “0x86” on the 1 byte at the desired baud rate in Table 6.7. See “Figure 6.13 Serial operation mode determination data”.

  • Page 94: Figure 6.14 Reception Flowchart In Serial Operation Mode

    TXZ Family Flash Memory use UART mode, or sometimes the data of the baud rate from the controller is not recognized. To avoid such situation, when UART mode is utilized, the controller should determine a time-out period where the time is expected to receive an echo-back “0x86”...

  • Page 95: Acknowledgement Response Data

    TXZ Family Flash Memory Figure 6.15 Serial operation mode determination flowchart 6.6.6.2. Acknowledgement Response Data The internal boot program represents processing states in specific codes and sends them to the controller. From “Table 6.8 ACK response data corresponding to serial operation determination data” to “Table 6.11 ACK response data corresponding to flash memory erasing operation”...

  • Page 96: Password

    TXZ Family Flash Memory Table 6.10 ACK response data corresponding to CHECKSUM data Transmit data Meaning A receive error occurred in the operation command 0xN8(Note) data. 0xN1(Note) A CHECKSUM error or password error occurred. The CHECKSUM value was determined as correct 0xN0(Note) value.

  • Page 97: Figure 6.16 Password Configuration (Example Of Transmission)

    If a password error occurs, from then on the external device cannot communicate with the TXZ. To communicate with the TXZ, perform reset with the reset pin (RESET_N) or Power On Reset(POR) to reboot the TXZ in single boot mode.

  • Page 98: Table 6.12 Password Setting Values And Setting Ranges

    TXZ Family Flash Memory (3) Password Setting/Releasing/Verification ･Password setting Password system uses a part of a user program. Therefore, special process is not required for password setting. At the time when a password is programmed to the code flash, a password is set.

  • Page 99: Password Determination

    TXZ Family Flash Memory 6.6.6.4. Password Determination (1) Password verification using RAM transfer command This item explains about the password determination No.5 described in “6.6.8. Communication Rules of RAM Transfer Command”. If password area data deviates from the range of address, a password address error occurs. Also, if the same three bytes data or more are continued, or the case where data is not all “0xFF”, a password error occurs as shown in...

  • Page 100: Communication Rules For Determination Of Serial Operation Mode

    This section describes the communication rule for determination of serial operation mode. Transfer directions in the table are indicated as follows: Transfer direction (CT): Controller to TXZ Transfer direction (TC): TXZ from controller Communication rules for determination of serial operation mode Table 6.13...

  • Page 101: Communication Rules Of Ram Transfer Command

    6.6.8. Communication Rules of RAM Transfer Command This section shows communication rules of RAM transfer. Transfer directions in the table are indicated as follows: Transfer direction (CT): From Controller to TXZ Transfer direction (TC): From TXZ to Controller Table 6.14 Communication Rules of RAM Transfer Command...
  • Page 102 TXZ Family Flash Memory CT RAM store start address (31 to 24) The controller transmits the RAM start address to be stored in RAM store data by dividing into 4 times as a next CT RAM store start address (23 to 16) transmit data.

  • Page 103: Communication Rules Of Flash Memory Erasing

    This section shows a communication format of flash memory erasing command. Transfer directions in the table are indicated as follows: Transfer direction (CT): From Controller to TXZ Transfer direction (TC): From TXZ to Controller Communication Rules of Flash memory Erasing Table 6.15...

  • Page 104: Internal Boot Program General Flowchart

    TXZ Family Flash Memory 6.6.10. Internal Boot Program General Flowchart This section shows an internal boot program general flowchart. UART Baud rate Detection Figure 6.18 Boot program general flowchart 104 / 120 2018-06-05 Rev. 2.0...

  • Page 105: Reprogramming Procedure Of The Flash Using Reprogramming Algorithm In Boot Rom

    TXZ Family Flash Memory 6.6.11. Reprogramming Procedure of the Flash Using Reprogramming Algorithm in Boot This section describes the reprogramming procedure of the flash using reprogramming algorithm in the on-chip Boot ROM. (The Following example is using UART) 6.6.11.1. Step-1 The condition of the flash memory does not care whether a former user program has been programmed or erased.

  • Page 106: Step-3

    TXZ Family Flash Memory 6.6.11.3. Step-3 When the password verification is completed, the boot program transfers a programming routine (a) from the host into the on-chip RAM. The Boot ROM loads this routine to the on-chip RAM. The programming routine must be stored in the range from “0x20000400”...

  • Page 107: Step-5

    TXZ Family Flash Memory 6.6.11.5. Step-5 The boot program executes the programming routine (a) to download new application program codes from the host and programs it into the erased flash area. When the programming is completed, set the programming or erasing protection of that flash area in the user’s program to ON.

  • Page 108: How To Reprogramming Using Dual Mode

    TXZ Family Flash Memory How to Reprogramming using Dual Mode The dual mode executes flash reprogramming using the flash memory reprogramming routine located in specified block on the users’ set. For example, while a program is executing on FLASH I/F 0, another area (such as Area 4 of FLASH I/F 2: data flash) of the flash memory, on which instructions are not executed, can be programmed/erased.

  • Page 109: Step-2

    TXZ Family Flash Memory 6.7.1.2. Step-2 This section explains the case where a programming routine is stored in the reset routine. The reset routine determines to enter the dual mode. If mode switching conditions are met, the program jumps to the flash reprogramming routine to transfer to dual mode.

  • Page 110: Step-4

    TXZ Family Flash Memory 6.7.1.4. Step-4 Subsequently, confirm whether the erased area of the flash are blank, and then downloads a new user’s application program data from the transfer source (Host) to develop it on the RAM. Developed data on the RAM is written to the erased area of the flash memory. When all data programming is completed, set the program/erase protection of that flash block in the user program area to ON.

  • Page 111: How To Reprogramming User Boot Program

    TXZ Family Flash Memory How to Reprogramming User Boot Program This method switches the Page 0 area to Page 1 area to hold a user boot program using the memory swap function when Flash memory is reprogrammed. The following is an example of reprogramming procedure of user boot program.

  • Page 112: Step-2

    TXZ Family Flash Memory 6.8.1.2. Step-2 The user checks [FCPSR0]<PG1>=0. If protection status enabled then write “0” to [FCPMR0]<PM1> for temporary release protection. Figure 6.31 Reprogram by User Boot Program (2) 6.8.1.3. Step-3 The user transfers the reprogramming routine to the on-chip RAM, and moves the PC (Program Counter) to the transferred program.

  • Page 113: Step-4

    TXZ Family Flash Memory 6.8.1.4. Step-4 The user erases Page 1, and then copy a program of Page 0 to program of Page 1. Figure 6.33 Reprogram by User Boot Program (4) 6.8.1.5. Step-5 The automatic memory swap command sets “01” to [FCSWPSR]<SWP[1:0]> to swap Page 0 with Page 1.

  • Page 114: Step-6

    TXZ Family Flash Memory 6.8.1.6. Step-6 The user performs a reset or releases a reset condition. Page 1 is assigned to address 0 and the flash memory boots up at Page1. A program branches to the conditioning routine where [FCSWPSR]<SWP[1:0]> is set to “01” (To [Step-7]).

  • Page 115: Step-8

    TXZ Family Flash Memory 6.8.1.8. Step-8 The user transfers the flash reprogramming routine to the on-chip RAM, and then sets the on-chip RAM address to PC (Program Counter). Figure 6.37 Reprogram by User Boot Program (8) 6.8.1.9. Step-9 The user programs a new boot program to Page 0.

  • Page 116: Step-10

    TXZ Family Flash Memory 6.8.1.10. Step-10 The automatic memory swap command sets “11” to [FCSWPSR]<SWP[1:0]> to swap release Page 0 and Page 1. Figure 6.39 Reprogram by User Boot Program (10) 116 / 120 2018-06-05 Rev. 2.0...

  • Page 117: General Precautions

    TXZ Family Flash Memory 7. General Precautions Do not perform any operation that is not described in this document.  Do not access the addresses described in this document that is not assigned to the registers.  117 / 120 2018-06-05 Rev.

  • Page 118: Revision History

    TXZ Family Flash Memory 8. Revision History Table 8.1 Revision history Revision Date Description First release 2018-01-22 - Conventions Modified “This flash memory” to “The flash memory” of arm trademarks - 1. Outline Added (Note) to Protection in Table1.1 Added 4KB to Flash memory in Table1.2 - 2.1 Block Diagrams...
  • Page 119 TXZ Family Flash Memory -5.2.21 [FCBUFDISCLR] Modified User Information Memory to User Information Area -6.6.6.3 Password Added number of (1) to (4) to subtitles Password releasing in (3) Password Setting/Releasing/Verification: Modified User Information Memory to User Information Area - 6.6.10 Internal Boot Program General Flowchart Modified “UART automatic Port Detection”...

  • Page 120: Restrictions On Product Use

    Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the instructions for the application with which the Product will be used with or for.

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