Toshiba TLCS-900/H1 Series Data Book page 59

(7)Notes
The instruction execution unit and the bus interface unit in this CPU operate independently.
Therefore if, immediately before an interrupt is generated, the CPU fetches an instruction which
clears the corresponding interrupt request flag, the CPU may execute this instruction in between
accepting the interrupt and reading the interrupt vector. In this case, the CPU will read the
default vector 0004H and jump to interrupt vector address FFFF04H.
To avoid this, an instruction which clears an interrupt request flag should always be preceded
by a DI instruction.
In addition, please note that the following two circuits are exceptional and demand special
attention.
INT0 Level Mode
INTRX
Note: The following instructions or pin input state changes are equivalent to instructions which clear
the interrupt request flag.
INT0: Instructions which switch to Level Mode after an interrupt request has been generated in
Edge Mode.
The pin input changes from High to Low after an interrupt request has been generated in
Level Mode. ("H" → "L")
INTRX: Instructions which read the Receive Buffer
In Level Mode INT0 is not an edge-triggered interrupt. Hence, in
Level Mode the interrupt request flip-flop for INT0 does not function.
The peripheral interrupt request passes through the S input of the
flip-flop and becomes the Q output. If the interrupt input mode is
changed from Edge Mode to Level Mode, the interrupt request flag is
cleared automatically.
If the CPU enters the interrupt response sequence as a result of
INT0 going from 0 to 1, INT0 must then be held at 1 until the interrupt
response sequence has been completed. If INT0 is set to Level Mode
so as to release a Halt state, INT0 must be held at 1 from the time
INT0 changes from 0 to 1 until the Halt state is released. (Hence, it is
necessary to ensure that input noise is not interpreted as a 0, causing
INT0 to revert to 0 before the Halt state has been released.)
When the mode changes from Level Mode to Edge Mode, interrupt
request flags which were set in Level Mode will not be cleared.
Interrupt request flags must be cleared using the following sequence.
DI
LD (IIMC), 00H; Switches from level to edge.
LD (INTCLR), 0AH; Clears interrupt request flag.
EI
In edge mode(the register SIMC<IRxLE> set to "0"),the interrupt
request flip-flop can only be cleared by a Reset or by reading the
Serial Channel Receive Buffer. It cannot be cleared by an instruction.
92CH21 - 55
TMP92CH21