Toshiba TLCS-900/H1 Series Data Book page 25

3.3.3 System clock controller
The system clock controller generates the system clock signal (f
internal I/O. It contains two oscillation circuits and a clock gear circuit for high-frequency (fc)
operation. The register SYSCR1<SYSCK> changes the system clock to either fc or fs,
SYSCR0<XEN> and SYSCR0<XTEN> control enabling and disabling of each oscillator, and
SYSCR1<GEAR2 to 0> sets the high-frequency clock gear to either 1, 2, 4, 8 or 16 (fc, fc/2, fc/4,
fc/8 or fc/16). These functions can reduce the power consumption of the equipment in which the
device is installed.
The combination of settings <XEN> = 1, <SYSCK> = 0 and <GEAR2 to 0> = 100
will cause the system clock (f
For example, f
X2 pins.
(1) Switching from Normal Mode to Slow Mode
When the resonator is connected to the X1 and X2 pins, or to the XT1 and XT2 pins, the
warm-up timer can be used to change the operation frequency after stable oscillation has
been attained.
The warm-up time can be selected using SYSCR2<WUPTM1 to 0>.
This warm-up timer can be programmed to start and stop as shown in the following
examples 1 and 2.
Table 3.3.2 shows the warm-up time.
Note 1: When using an oscillator (other than a resonator) with stable oscillation, a warm-up
timer is not needed.
Note 2: The warm-up timer is operated by an oscillation clock. Hence, there may be some
variation in warm-up time.
Warming-up Time
SYSCR2
<WUPTM1,WUPTM0>
8
01 (2 / frequency)
14
10 (2 / frequency)
16
11 (2 / frequency)
) to be set to fc/32 (fc/16×1/2) after reset.
SYS
is set to 1.25 MHz when the 40MHz oscillator is connected to the X1 and
SYS
Table 3.3.2 Warming-up times
Change to
Normal Mode
6.4 (µs)
409.6 (µs)
1.638 (ms)
92CH21 - 21
TMP92CH21
) for the CPU core and
SYS
at f = 40MHz, fs = 32.768 kHz
OSCH
Change to
Slow Mode
7.8 (ms)
500 (ms)
2000 (ms)