Toshiba TLCS-900/H1 Series Data Book page 342

3.14.4 TFT color display mode
3.14.4.1 Description of operation
It is basically same setting to SR mode.
Set the mode of operation, start address of source data save memory, color level and LCD size
to control registers before setting start register.
After set start register, LCDC outputs bus release request to CPU and read data from source
memory. After finish data read from source data, LCDC cancels the bus release request and CPU
will re-start. After that LCDC transmits data of volume of LCD size to external LCD driver through
LD bus (Special data bus for only LCDD). At this time, control signals (LCP0 etc.) connected LCD
driver output specified waveform synchronizes with data transmission.
TFT mode LCDC, during data read from source memory (during DMA operation), CPU is
stopped by internal BUSREQ signal.
LCD controller generates some control signals (LFR, LBCD, LLP etc) from base clock: LCDSCC.
LCDSCC is base clock for LCD controller, made from system clock: f
For TFT source driver, support these signals: 8bitRGB or 4bit*RGB special data bus and LCP0,
LFR, LLP and LDIV.
And for TFT gate driver control, LCP1, LBCD and LGOE2 to 0.
3.14.4.2 Memory space
Memory space setting is same to SR mode. Refer to SR mode.
3.14.4.3 Mapping of display memory and panning function
Panning function and display memory mapping are same to SR mode. Refer to SR mode.
3.14.4.4 Data transmission
TMP91CH21 out display data form special bus for LCDD. And we can select that width for input
width of LCDD. 8bit and 12bit width is supported.
Under Development
92CH21-338
TMP92CH21
SYS.