Toshiba TLCS-900/H1 Series Data Book page 485

(11) UART/Serial Channel(1/2)
Symbol Name
Serial
Channel 0
SC0BUF
Buffer
Register
Serial
Channel 0
SC0CR
Control
Register
Serial
Channel 0
SC0MOD0
Mode 0
Register
Serial
Channel 0
BR0CR
Baud Rate
Control
Register
Serial
Channel 0
BR0ADD
K setting
Register
Serial
Channel 0
SC0MOD1
Mode 1
Register
IrDA
SIRCR
Control
Register
Address 7
RB7 RB6
TB7 TB6
1200H
RB8 EVEN
R
0
1201H
Receive Parity
data 0:Odd
bit 8 1:Even
TB8 CTSE
0
Trans-mis 0:CTS
1202H
sion data Disable
bit 8 1:CTS
Enable
-
BR0ADDE
0
1203H
Fix to "0" (16-K)/16
divided
0:Disable
1:Enable
1204H
-
I2S0 FDPX0
R/W R/W
0
1205H
I/O interface
IDLE2
mode
0:Stop
1:Full duplex
1:Operate
0:Half duplex
PLSEL RXSEL
0
Select Receive
1207H
transmit data
pulse width 0:
0:3/16 pulse
1:1/16 1: "L" pulse
6 5 4
RB5 RB4
TB5 TB4
R(Receiving) / W(Transmission)
PE OERR
R/W R (Clear 0 after reading)
0 0 0
Parity
0:Disable
Overrun
1:Enable
RXE WU
0 0 0
0:Receive Wake up
Disable 0:Disable
1:Receive 1:Enable
Enable
BR0CK1 BR0CK0
0 0 0
00:φT0
01:φT2
10:φT8
11:φT32
- - -
0 - -
TXEN RXEN
0 0 0
Transmit Receive
0: disable 0: disable
"H" 1: enable 1: enable
92CH21 - 482
3 2
RB3 RB2
TB3 TB2
Undefined
PERR FERR
0 0
1:Error
Parity Framing
SM1 SM0
R/W
0 0
00:I/O Interface
Mode
01:7bit UART Mode
10:8bit UART Mode
11:9bit UART Mode
BR0S3 BR0S2
R/W
0 0
Set the frequency divisor "N"
BR0K3 BR0K2
0 0
Set the frequency divisor "K" (1 to F)
- -
SIRWD3 SIRWD2
R/W
0 0
Select receive pulse width
Set effective pulse width for equal or more than
2x × x (value + 1)
Can be set : 1 to 4
Can not be set : 0, 15
TMP92CH21
1 0
RB1 RB0
TB1 TB0
SCLKS IOC
R/W
0 0
0: Baud
0:SCLK0↑
Rate
1:SCLK0↓
Generator
1:SCLK0
Pin Input
SC1 SC0
0 0
00:TimerTOTRG
01:
Baud Rate Generator
10:Internal clock φ１
11:External clock
(SCLK0 Input)
BR0S1 BR0S0
0 0
0 to F
BR0K1 BR0K0
R/W
0 0
- -
SIRWD1 SIRWD0
0 0