Toshiba TLCS-900/H1 Series Data Book page 297

3.12.2 Control registers
The watchdog timer WDT is controlled by tow control registers WDMOD and WDCR .
(1) Watchdog Timer Mode Register (WDMOD)
!
Setting the detection time for the watchdog timer in <WDTP1,WDTP0>
This 2-bit register is used for setting the watchdog timer interrupt time used when detecting runaway.
On a Reset this register is initialized to WDMOD<WDTP1,WDTP0> = 00.
The detection times for WDT is 2
"
Watchdog timer enable/disable control register <WDTE>
At reset, the WDMOD<WDTE> is initialized to 1, enabling the watchdog timer.
To disable the watchdog timer, it is necessary to set this bit to 0 and to write the disable code (B1H)
to the Watchdog Timer Control Register WDCR. This makes it difficult for the watchdog timer to be
disabled by runaway.
However, it is possible to return the watchdog timer from the disabled state to the enabled state
merely by setting <WDTE> to 1.
#
Watchdog timer out reset connection <RESCR>
This register is used to connect the output of the watchdog timer with the RESET terminal internally.
Since WDMOD<RESCR>is initialized to 0 at reset, a reset by the watchdog timer will not be
performed.
(2) Watchdog Timer Control Register (WDCR)
This register is used to disable and clear the binary counter for the watchdog timer.
•
Disable control
The watchdog timer can be disabled by clearing WDMOD<WDTE> to 0 and then writing the
disable code (B1H) to the WDCR register.
WDMOD
WDCR
•
Enable control
Set WDMOD<WDTE>to 1.
•
Watchdog timer clear control
To clear the binary counter and cause counting to resume, write the clear code (4EH) to the
WDCR register.
WDCR
16
/fsys [S]. (The number of system clocks is approximately 65,536.)
← 0 - - - - - - -
← 1 0 1 1 0 0 0 1
← 0 1 0 0 1 1 1 0
92CH21- 293
Clear WDMOD<WDTE> to 0.
Write the disable code (B1H).
Write the clear code (4EH).
TMP92CH21