Osc_Clk_1 Clock Input - Intel Agilex Series Configuration User Manual

2. Intel Agilex Configuration Details
683673 | 2021.10.29
4. Click OK to confirm and close the Device and Pin Options.

2.6.2. OSC_CLK_1 Clock Input

OSC_CLK_1 Requirements
When you drive the
software, the device loads the majority of the configuration bitstream at 250 MHz. Intel Agilex devices include an internal
oscillator in addition to
devices always use this internal oscillator to load the first section of the bitstream, up to a maximum of 512 kilobyte (KB).
The SDM can use either clock source for the remainder of device configuration. If you use the internal oscillator, you can leave
the
OSC_CLK_1
When you specify
When you specify AS configuration scheme and
the POR state. Ensure the
you need to supply a stable free-running clock before/at the same time V
Send Feedback
input clock with an external clock source and enable
OSC_CLK_1
which runs the configuration process at a frequency between 160-230 MHz. Intel Agilex
OSC_CLK_1
unconnected. If you use transceivers, you must provide an external clock to this pin.
for configuration, the
OSC_CLK_1
clock is available before SDM starts to load the bitstream from the quad SPI flash or
OSC_CLK_1
clock must be a stable and free-running clock.
OSC_CLK_1
is pull high, the SDM starts the configuration once the device exits
nCONFIG
CCIO_SDM
in the Intel Quartus Prime
OSC_CLK_1
ramps up to the typical voltage level.
Intel ® Agilex ™ Configuration User Guide
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