Lcd Controller/Driver Control Registers; Figure 15-3: Lcd Display Mode Register (Lcdm) Format - NEC V850E/CA1 ATOMIC Preliminary User's Manual

32-/16-bit single-chip microcontroller
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15.3 LCD Controller/Driver Control Registers

The LCD controller/driver is controlled by the following register.
• LCD display mode register (LCDM)
(1)
LCD display mode register (LCDM)
This register sets display operation enabling/disabling, the LCD clock, frame frequency.
The LCDM register can be read or written in 1-bit or 16-bit units.

Figure 15-3: LCD Display Mode Register (LCDM) Format

15
14
13
LCDM LCDON ECOM ASTOP LIPS
Bit Name
LCDON
Display control bit (Output enable of the displayed data)
0: Display OFF
1: Display ON
If the display is switched off, the non-selected waveform will be output from the segment pin
regardless of the contents of the display data memory. If the display is switched on, either the
selected waveform or the non-selected waveform will be output from the segment pin according
to the contents of the display data memory.
ECOM
Common enable signal
0: Common disable
1: Common enable
This bit is used for common enabling. Before starting LCD make sure to set bit to 1. And in case
application requires low power, this bit should be disabled.
ASTOP
Driving power supply
0: All analog macro is working
1: LEPSB being used for STOP signal for analog
Note:
This is a bit which disable the whole analog macro. (Driving power supply.)
LIPS
Driving power supply
0: Internal driving power supply OFF
1: Internal driving power supply ON
Note:
This is a bit which authorizes/inhibits the common output and the segment output by the
internal power supply and the external power supply.
LCDM2,
Display mode select bit
LCDM1,
LCDM2
LCDM0
0
0
0
0
1
LCDC1,
Selection of LCD frame frequency
LCDC0
LCDC1
Note:
Frequency values if input clock of LCDC section is 31.25 KHz. (4 MHz/2
Chapter 15 LCD Controller/Driver
12
11
10
9
8
0
LCDM2 LCDM1 LCDM0
LCDM1
LCDM0
0
0
0
1
1
0
1
1
0
0
LCDC0
0
0
0
1
1
0
1
1
Preliminary User's Manual U14913EE1V0UM00
7
6
5
4
3
0
0
0
0
0
Function
No of time divisions
4
3
2
3
Division of f
CKSEL1
6
2
divisions
7
2
divisions
8
2
divisions
9
2
divisions
2
1
0
Address
0
LCDC1 LCDC0 FFFFF710H 0000H
Bias method
1/3
1/3
1/2
1/2
Static
Frame frequency(static)
488 Hz
244 Hz
122 Hz
61 Hz
7
)
At
Reset
515

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