Figure A-13. Receive Section Of The Asymmetrical Loop Timing Block Diagram - Comtech EF Data SDM-300A Installation And Operation Manual

SDM-300A Satellite Modem
R XD
RT
M C
TT
Note: PLL will be bypassed when the RX data rate is set to the TX data rate. This will disable
the Asymmetrical Mode.

Figure A-13. Receive Section of the Asymmetrical Loop Timing Block Diagram

Example:
Master/Slave Clocking Setup:
1. Master site has a 10 MHz clock that is needed as the clock source.
2. Unequal data rates: 4.096 Mbit/s and 2.152 Mbit/s (numbers divisible by 8).
Master Site Option:
1. Set Configuration/Modulator/Modem Reference to EXT 10 MHz.
2. Set Configuration/Interface/TX Clock Source to SCT (Internal).
Note: The SCT clock is slaved off the 10 MHz input. The 10 MHz reference should
be placed into CP3 of the modem.
3. Set Configuration/Interface/Buffer Clock to SCT (Internal).
Rev. 4
B UF
S AT
P LL
E XT
IN T
D D S
TE R R
Options
R XD
R XC
IN T
E XT
R EF
A–57