Comtech EF Data SDM-300A Installation And Operation Manual page 240

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SDM-300A Satellite Modem
IBS
IBS operation adds a proportional overhead (1/15) to the terrestrial data. The terrestrial
data and clock are passed through the baseband loopback relay and are translated from
the selected baseband format to Transistor-Transistor Logic (TTL). The data is scrambled
synchronously with the multiframe sync in the multiplexer. The scrambler is enabled
using the front panel.
External input and output for an ESC in EIA-232 format is provided on the interface. The
ESC runs asynchronously at approximately 1/2000 of the terrestrial data rate. If the ESC
clock is used, the channel runs at 1/512 of the terrestrial data rate. The overhead
containing framing, the ESC channel, and faults from the modem are multiplexed with
dejittered terrestrial data. The multiplexed data stream is output to the modulator through
the interface loopback device.
The receive data from the demodulator is input through the same interface loopback
device. The receive data is demultiplexed and synchronously descrambled by the
demultiplexer. The backward alarm is reported to the M&C and output by Form C relay
contact. The ESC is output by an EIA-232 driver. The terrestrial data output from the
demultiplexer is input to a plesiochronous buffer.
The front panel interface provides four clock selections clocking the data out of the
buffer:
If either RXCLK or EXT is selected and then fails, the interface automatically switches
to SCT as the source.
AIS is detected in the receive data and reported to the M&C.
The receive data and selected clock are translated to the levels of the selected baseband
interface and output through the baseband loopback relay.
The octet path is used for transferring a clock pulse to the distant end terrestrial
equipment. The clock pulse rate is the IBS data rate ÷ 8.
Refer to Figure A-11 for a block diagram of the IBS interface.
Rev. 4
Internal Clock (SCT)
RX Recovered Clock (RXCLK)
External Reference Clock (EXT)
High Stability Clock (HI STAB)
TX Clock Dejittered (TXCLK)
Options
A–51

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