Expansion Jtag Jumper (39); Bank 3 Voltage Selection (40); Iic Bus With 4Kb Eeprom (41) - Xilinx SP305 Spartan-3 User Manual

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Expansion JTAG Jumper (39)

The J26 Jumper connects the Expansion header to the JTAG chain.
Table 2-31: Expansion JTAG Jumper Connections

Bank 3 Voltage selection (40)

The J29 Jumper connects 3.3 0r 2.5 volts to the FPGA I/O Bank 3. The I/O it controls are the
Expansion Header 3 and 6.
Table 2-32: Bank 3 I/O Voltage Selection

IIC Bus with 4Kb EEPROM (41)

An IIC EEPROM (Microchip Technology 24LC04B-I/ST) is provided on the SP-305 board
to store non-volatile data such as an Ethernet MAC address. The EEPROM write protect is
tied off on the board to disable its hardware write protect. The IIC bus utilizes 2.5V
signaling and can operate at up to 400 kHz. IIC bus pull-up resistors are provided on the
board.
The IIC bus is extended to the expansion connector so that the user may add additional IIC
devices and share the IIC controller in the FPGA. If the expansion IIC bus is to be utilized,
the user must have additional IIC pull-up resistors present on the expansion card.
Bidirectional level shifting transistors allow the expansion card to utilize 2.5V to 5V
signaling on IIC.
Table 2-33: IIC FPGA Pins
SP305 Spartan-3 Development Platform User Guide
UG216 (v1.1) March 3, 2006
Label
FPGA_TDO to TDO
EPANSION_TDO to TDO
Label
2.5 Volts
3.3Volts
Label
IIC_SCL
IIC_SDA
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DESCRIPTION
No Expansion Header in
JTAG Chain
Expansion Header in JTAG
Chain
DESCRIPTION
2.5 Volts on Bank 3
3.3 Volts on Bank 3
FPGA Pin
D14
E14
Detailed Description
Jumper Pin
J26 1,2
J26 2,3
Jumper Pin
J29 1,2
J29 2,3
Description
IIC clock
IIC Data
35