Iic Bus - Xilinx SP605 Hardware User's Manual

Chapter 1: SP605 Evaluation Board

14. IIC Bus

The SP605 implements three IIC bus interfaces at the FPGA.
The MAIN IIC bus hosts four items:
•
•
•
•
The DVI IIC bus hosts two items:
•
•
The SFP IIC bus hosts two items:
•
•
The SP605 IIC bus topology is shown in
X-Ref Target - Figure 1-11
U1
IIC_SDA_MAIN
BANK 1
IIC_SCL_MAIN
IIC_SDA_SFP
BANK 0 IIC_SCL_SFP
IIC_SDA_DVI
BANK 2
IIC_SCL_DVI
P3
DVI Connector
IIC_SDA_DVI_F
Addr: 0b1010000
U31
DVI CODEC
CHRONTEL
CH730C-TF
Addr: 0b1110110
38
FPGA U1 Bank 1 "MAIN" IIC interface
8-Kb NV Memory U4
FMC LPC connector J2
2-Pin External Access Header J45
FPGA U1 Bank 2 DVI IIC interface
DVI Codec U31 and DVI connector P3
FPGA U1 Bank 0 SFP IIC interface
SFP module connector P2
LEVEL
SHIFTER
IIC_CLK_DVI_F
Figure 1-11: IIC Bus Topology
www.xilinx.com
Figure 1-11.
SP605 Hardware User Guide
UG526 (v1.9) February 14, 2019
U4
ST MICRO
M24C08-WDW6TP
Addr: 0b1010100
through
0b1010111
J2
FMC LPC
Column C
2 Kb EEPROM on
any FMC LPC
Mezzanine Card
Addr: 0b1010010
J45
2-Pin External
Access Header
P2
SFP Module
Connector
Addr: 0b1010000
UG526_11_092609