System Memory Interface; Overview - Intel PXA27 Series Design Manual

System Memory Interface

This chapter describes guidelines for interfacing with the memory controller of Intel
Processor Family (PXA27x processor) to external memory. See examples of schematics and timing
diagrams for SDRAM, SRAM, flash, and PC Card devices.
6.1

Overview

The external memory bus interface for the PXA27x processor supports:
•
SDRAM (100 MHz at 3.3 V, 3.0 V, 2.5 V, and 1.8 V)
•
Flash (synchronous and asynchronous burst mode and page mode)
•
ROM (page mode)
•
SRAM (including variable latency I/O (VLIO) devices)
•
PC Card (PCMCIA)/Compact Flash
In addition to supporting the memory types listed above, the memory controller of the PXA27x
processor lets an alternate bus master request the bus and gain access to the SDRAM in partition 0.
See Table 6-1
cells in Table 6-1
independently configured. Refer to the memory chapter in the Intel
Developers Manual on how to configure the SDRAM and static memory alternate memory map
locations.
Mbytes
Table 6-1. Memory Address Map (Sheet 1 of 2)
Address
0x0000_0000
0x0400_0000
0x0800_0000
0x0C00_0000
0x1000_0000
0x1400_0000
0x2000_0000
0x3000_0000
®
Intel PXA27x Processor Design Guide
for the physical addresses used to configure and map the external memory. Shaded
indicate no alternate address mapping available. SDRAM and static memory are
Mapped Function
Static Chip Select 0
(64 Mbytes max)
Static Chip Select 1
(64 Mbytes max)
Static Chip Select 2
(64 Mbytes max)
Static Chip Select 3
(64 Mbytes max)
Static Chip Select 4
(64 Mbytes max)
Static Chip Select 5
(64 Mbytes max)
PCMCIA/CF Slot 0 (256
Mbytes)
PCMCIA/CF Slot 1 (256
Mbytes)
®
PXA27x Processor Family
Alternate Alternate Mapped
Address Locations
0x0000_0000
Static Chip Select 0
(128 Mbytes max)
0x0800_0000
Static Chip Select 1
(128 Mbytes max)
Static Chip Select 4
0x1000_0000
(64 Mbytes max)
Static Chip Select 5
0x1400_0000
(64 Mbytes max)
0x2000_0000 PCMCIA/CF Slot 0
(256 Mbytes)
0x3000_0000 PCMCIA/CF Slot 1
(256 Mbytes)
6
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PXA27x
II:6-1